Data-weighted element mismatch shaping in digital to analog converters

An element rotation selection (ERS) system for mismatch shaping, the ERS system comprising:

• a first sub-ERS logic;
• a second sub-ERS logic;
• a first DAC coupled to the first sub-ERS logic;
• a second DAC coupled to the second sub-ERS logic, wherein the first and second DACs are to receive an output of the first and second sub-ERS logics to perform a digital to analog conversion;
• and
• a data-weighted sigma-delta (SD) modulator configured to:
• monitor a difference between a data weight of the first and second sub-ERS logic;
• and
• select either the first or the second sub-ERS logic to maintain substantially equal usage over time between the first sub-ERS logic and the second sub-ERS logic.

A non-transitory computer readable storage medium storing software code portions configured, when executed on a processor, for mismatch shaping for a digital to analog converter, by:

• splitting an original input of a circuit into a plurality of time interleaved data streams;
• directing one of the plurality of time interleaved data streams to element rotation selection (ERS) logic according to a decision of a data-weighted sigma-delta (SD) modulator;
• and
• processing, using the ERS logic, the directed one of the plurality of time interleaved data streams.