# US 12,119,831 B2 · Ultra-low power instant lock phase lock loop (PLL) > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,831 B2 - Document ID: US12119831B2 - Status: Granted - Kind: B2 - Application number: 18/113,601 - Filed: 2023-02-23 - Published: 2023-10-12 - Granted: 2024-10-15 - Earliest claimed: 2022-04-07 - Assignees: Maxim Integrated Products, Inc. - Applicants: Maxim Integrated Products, Inc. - Inventors: Cheng-Hsien Hung; Chun-Wei Hsu; ChunCheng Chou - Web page: https://patentgrep.com/patent/US12119831B2 ## CPC - H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) - H03L 7/0992: {comprising a counter or a frequency divider} - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - H03L 2207/50: All digital phase-locked loop - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal. ## Claims ### Claim 1 An all-digital phase-locked loop (ADPLL) circuit comprising: a time-to-digital converter (TDC) comprising a first input and a second input, the TDC generates a quantized output that represents a phase difference between the first input and the second input; a digital phase compensation circuit that performs steps comprising generating an adjusted quantized output representative of a substantially zero phase difference between the first input and the second input; a digitally controlled oscillator (DCO) that, in response to receiving the adjusted quantized output and a target frequency, generates a DCO output signal, the DCO obtains the target frequency from a calibration made using an open loop circuit configuration; and a feedback path that uses a feedback signal to couple the DCO output signal to the second input. ### Claim 2 (depends on 1) The ADPLL according to claim 1, further comprising a frequency divider coupled to the second input, the frequency divider subsamples the DCO output signal to generate a first clock signal that has a first clock frequency that is lower than a reference frequency of a reference signal. ### Claim 3 (depends on 2) The ADPLL according to claim 2, wherein the frequency divider subsamples the DCO output signal in response to receiving a rising edge of the DCO output signal that operates at the target frequency and a rising edge of the reference signal that comprises the reference frequency. ### Claim 4 (depends on 2) The ADPLL according to claim 2, further comprising a digital-to-time converter (DTC) that, in response to receiving a second clock signal comprising a second clock frequency, generates the reference signal. ### Claim 5 (depends on 1) The APLL according to claim 1, wherein the feedback path comprises a frequency divider that, in response to receiving the DCO output signal, generates the feedback signal. ### Claim 6 (depends on 1) The APLL according to claim 1, wherein the calibration is performed in a power-up phase. ### Claim 7 (depends on 1) The APLL according to claim 1, wherein the calibration uses a control signal to generate a digital code that causes the DCO to operate at the target frequency. ### Claim 8 (depends on 7) The APLL according to claim 7, wherein the control signal is generated by a loop filter circuit coupled to digital phase compensation circuit. ### Claim 9 (depends on 8) The ADPLL according to claim 8, wherein the loop filter circuit attenuates at least one of a high-frequency noise or a phase noise in the adjusted quantized output. ### Claim 10 A method for reducing a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit, the method comprising: receiving a reference signal having a reference frequency; setting a digitally controlled oscillator (DCO) to a target frequency that is greater, by a factor, than the reference frequency, the DCO generating an output signal, the target frequency is obtained from a calibration made using an open loop circuit configuration; using the output signal to generate a feedback signal; using a time-to-digital converter (TDC) to determine an initial phase difference between the reference signal and the feedback signal; and using a digital initial phase compensation circuit that adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal. ### Claim 11 (depends on 10) The method according to claim 10, wherein the initial phase difference is defined by a time difference between a rising edge of the feedback signal that is closest to a rising edge of the reference signal. ### Claim 12 (depends on 10) The method according to claim 10, wherein the calibration is performed in a power-up phase of the APLL. ### Claim 13 (depends on 10) The method according to claim 10, wherein the calibration generates a digital code that causes the DCO to operate at the target frequency. ### Claim 14 (depends on 13) The method according to claim 13, wherein the calibration uses a control signal to generate the digital code. ### Claim 15 (depends on 14) The method according to claim 14, wherein the control signal is generated by a loop filter circuit coupled to digital phase compensation circuit. ### Claim 16 (depends on 15) The method according to claim 15, wherein the loop filter circuit attenuates at least one of a high-frequency noise or a phase noise. ### Claim 17 (depends on 10) The method according to claim 10, wherein the DCO output signal is divided by a frequency divider located in a feedback path. ### Claim 18 (depends on 17) The method according to claim 17, wherein the frequency divider generates the feedback signal in response to receiving the DCO output signal.