# US 12,119,827 B2 · Glitch filter with reset circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,827 B2 - Document ID: US12119827B2 - Status: Granted - Kind: B2 - Application number: 18/087,731 - Filed: 2022-12-22 - Published: 2024-06-27 - Granted: 2024-10-15 - Earliest claimed: 2022-12-22 - Assignees: Synopsys, Inc. - Applicants: Synopsys, Inc. - Inventors: Kailash Kumar; Prateek Singh; Akhil Thotli; Sriram Kumar Jayanthi; Rahul Gupta - Web page: https://patentgrep.com/patent/US12119827B2 ## CPC - H03K 5/1252: Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) - H03K 17/16: Modifications for eliminating interference voltages or currents - H03K 19/003: Modifications for increasing the reliability {for protection} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An electric circuit and a method for filtering glitches are described. The electric circuit includes a filter, an inverter circuit, and a reset circuit. The inverter circuit is electrically coupled to an output of the filter. The reset circuit is electrically coupled to the output of the filter. The reset circuit pulls the output of the filter high when an input signal to the electric circuit and the output of the inverter circuit are both low, pulls the output of the filter low when the input signal to the electric circuit and the output of the inverter circuit are both high, and passes the output of the filter when (i) the input signal to the electric circuit is high and the output of the inverter circuit is low or (ii) the input signal to the electric circuit is low and the output of the inverter circuit is high. ## Claims ### Claim 1 An electric circuit for filtering glitches, the electric circuit comprising: a filter; an inverter circuit electrically coupled to an output of the filter; and a reset circuit electrically coupled to the output of the filter, wherein the reset circuit is arranged to: pull the output of the filter high when an input signal to the electric circuit and the output of the inverter circuit are both low; pull the output of the filter low when the input signal to the electric circuit and the output of the inverter circuit are both high; and pass the output of the filter when (i) the input signal to the electric circuit is high and the output of the inverter circuit is low or (ii) the input signal to the electric circuit is low and the output of the inverter circuit is high. ### Claim 2 (depends on 1) The electric circuit of claim 1, further comprising a bypass inverter arranged to: invert the input signal to the electric circuit when the filter is disabled; and turn off when the filter is enabled. ### Claim 3 (depends on 2) The electric circuit of claim 2, wherein the inverter circuit comprises: a first inverter electrically coupled to the output of the filter; a second inverter electrically coupled to an output of the first inverter; and a third inverter electrically coupled to an output of the second inverter. ### Claim 4 (depends on 3) The electric circuit of claim 3, wherein an output of the bypass inverter is electrically coupled to the output of the second inverter. ### Claim 5 (depends on 3) The electric circuit of claim 3, wherein the second inverter is arranged to: invert the output of the first inverter when the filter is enabled; and turn off when the filter is disabled. ### Claim 6 (depends on 1) The electric circuit of claim 1, further comprising a synchronizer circuit arranged to: electrically disconnect the filter from the reset circuit when the filter is disabled; and electrically connect the filter to the reset circuit when the filter is enabled. ### Claim 7 (depends on 1) The electric circuit of claim 1, further comprising an input inverter arranged to: invert the input signal to the electric circuit when the filter is enabled, wherein the filter is electrically coupled to an output of the input inverter; and turn off when the filter is disabled. ### Claim 8 A method for filtering glitches, the method comprising: pulling, by a reset circuit, an output of a filter high when an input signal and an output of an inverter circuit are both low, wherein the inverter circuit and the reset circuit are electrically coupled to the output of the filter; pulling, by the reset circuit, the output of the filter low when the input signal and the output of the inverter circuit are both high; and passing the output of the filter when (i) the input signal is high and the output of the inverter circuit is low or (ii) the input signal is low and the output of the inverter circuit is high. ### Claim 9 (depends on 8) The method of claim 8, further comprising: inverting, by a bypass inverter, the input signal when the filter is disabled; and turning off the bypass inverter when the filter is enabled. ### Claim 10 (depends on 9) The method of claim 9, wherein the inverter circuit comprises: a first inverter electrically coupled to the output of the filter; a second inverter electrically coupled to an output of the first inverter; and a third inverter electrically coupled to an output of the second inverter. ### Claim 11 (depends on 10) The method of claim 10, wherein an output of the bypass inverter is electrically coupled to the output of the second inverter. ### Claim 12 (depends on 10) The method of claim 10, further comprising: inverting, by the second inverter, the output of the first inverter when the filter is enabled; and turning off the second inverter when the filter is disabled. ### Claim 13 (depends on 8) The method of claim 8, further comprising: electrically disconnecting, by a synchronizer circuit, the filter from the reset circuit when the filter is disabled; and electrically connecting, by the synchronizer circuit, the filter to the reset circuit when the filter is enabled. ### Claim 14 (depends on 8) The method of claim 8, further comprising: inverting, by an input inverter, the input signal when the filter is enabled, wherein the filter is electrically coupled to an output of the input inverter; and turning off the input inverter when the filter is disabled.