# US 12,119,826 B2 · Embedded pattern generator

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- Number: US 12,119,826 B2
- Document ID: US12119826B2
- Status: Granted
- Kind: B2
- Application number: 17/849,417
- Filed: 2022-06-24
- Published: 2022-12-29
- Granted: 2024-10-15
- Earliest claimed: 2021-06-25
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Srinivasa Chakravarthy; Prasanth Viswanathan Pillai; Mohammed Arif; Bhargov Bora
- Web page: https://patentgrep.com/patent/US12119826B2

## CPC

- H03K 5/00006: {Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68)}
- G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)}
- G06F 11/263: Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers}
- H03K 21/02: Input circuits
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An example apparatus includes multiplexer circuitry configured to couple a communication module to at least one of a data bus input or a test signal; and embedded pattern generator (EPG) circuitry coupled to the multiplexer circuitry, the EPG circuitry including: clock divider circuitry including a plurality of clock outputs, the clock divider circuitry configured to be coupled to an output of a clock, the plurality of clock outputs configured to be of a frequency equal to a division of a frequency of the output of the clock; a multiplexer including a multiplexer output, the multiplexer configured to couple one of the plurality of clock outputs to the multiplexer output; and signal generator circuitry including an input clock, an EPG input, and a plurality of data outputs, the input clock coupled to the multiplexer output, the signal generator circuitry configured to generate a data stream.

## Claims

### Claim 1

A device comprising:
multiplexer circuitry configured to couple a communication module to at least one of a data bus input or a test signal; and
embedded pattern generator (EPG) circuitry coupled to the multiplexer circuitry, the EPG circuitry including:
clock divider circuitry including a plurality of clock outputs, the clock divider circuitry configured to be coupled to an output of a clock, the plurality of clock outputs configured to be of a frequency equal to a division of a frequency of the output of the clock;
a multiplexer including a multiplexer output, the multiplexer configured to couple one of the plurality of clock outputs to the multiplexer output; and
signal generator circuitry including an input clock, an EPG input, and a plurality of data outputs, the input clock coupled to the multiplexer output, the signal generator circuitry configured to generate a data stream.

### Claim 2 (depends on 1)

The device of claim 1, further including a controller coupled to the multiplexer circuitry and the EPG circuitry, the controller configured to control which of the plurality of clock outputs are coupled to the input clock of the signal generator circuitry and to control which of a plurality of outputs of the EPG circuitry are coupled to the communication module.

### Claim 3 (depends on 1)

The device of claim 1, wherein the multiplexer circuitry is configured to couple the data stream to the communication module to perform at least one of a test, a debugging, or a diagnostic test of one or more of the communication module.

### Claim 4 (depends on 1)

The device of claim 1, wherein the EPG circuitry is coupled to an EPG input signal including a plurality of bits configured to be shifted into the signal generator circuitry.

### Claim 5 (depends on 1)

The device of claim 1, wherein the clock divider circuitry includes a clock divider counter configured to divide the output of the clock by one or more counter values to generate one or more divided versions of the output of the clock on the plurality of clock outputs.

### Claim 6 (depends on 1)

The device of claim 1, wherein the clock divider circuitry is a first clock divider circuitry, the multiplexer is a first multiplexer, and the signal generator circuitry is a first signal generator circuitry, the EPG circuitry further includes a second clock divider circuitry, a second multiplexer, and a second signal generator circuitry, the second multiplexer configured to couple one of a plurality of clock signal outputs of the second clock divider circuitry to an input of the second signal generator circuitry.

### Claim 7 (depends on 1)

The device of claim 1, wherein the multiplexer is a first multiplexer, the EPG circuitry further including a second multiplexer configured to couple one of the plurality of clock outputs or the plurality of data outputs to the data stream.

### Claim 8

An apparatus comprising:
clock divider circuitry including a clock input and a counter input, the clock divider circuitry to generate a plurality of output clocks based on the clock input and the counter input;
signal generator circuitry to generate a test signal based on a plurality of inputs and a clock input;
a controller to at least:
select a frequency of the plurality of output clocks as a result of supplying a counter value to the counter input;
select a data rate of the test signal by controlling a multiplexer to couple one of the plurality of output clocks to the clock input;
select a value of the test signal as a result of supplying an embedded pattern generator (EPG) input to the plurality of inputs; and
configure multiplexer circuitry to couple one of the test signal or the plurality of clock outputs to an input of communication circuitry.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the clock divider circuitry is configured to divide the clock input to generate the plurality of output clocks based on the counter value provided by the controller.

### Claim 10 (depends on 8)

The apparatus of claim 8, wherein the clock divider circuitry includes a plurality of clock dividers including:
clock stop circuitry configured to generate a run clock output based on the clock input and a clock enable input, the clock enable input to enable the run clock output; and
clock divider counter coupled to the run clock output, the clock divider configured to divide the run clock output by the counter value provided by the controller.

### Claim 11 (depends on 8)

The apparatus of claim 8, wherein the signal generator circuitry transforms a first value based on a transform operation determined by the controller, the transform operation to cause the signal generator circuitry to perform at least one of a hold operation to hold the first value, an update operation to update the first value based on the plurality of inputs, a shift operation to bit shift the first value, or a copy operation to set the first value to a second value.

### Claim 12 (depends on 8)

The apparatus of claim 8, wherein the multiplexer circuitry is a first multiplexer circuitry, the signal generator circuitry includes:
a register including a value, the register to be modified based on the clock input;
a second multiplexer circuitry couples one of the plurality of inputs, the value, or a transformed data value to an input of the register;
data transform circuitry to transform the value based on a transform operation set by the controller to generate a transform output; and
a third multiplexer circuitry couples at least one of the value or a bit reversed version of the value to the data transform circuitry.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the signal generator circuitry is further configured to include a fifth multiplexer circuitry configured to couple the transform output of the data transform circuitry to the test signal based on the controller.

### Claim 14 (depends on 8)

The apparatus of claim 8, wherein the controller is further configured to test the communication circuitry by supplying the test signal to the communication circuitry.

### Claim 15

A method comprising:
generating, by embedded pattern generator (EPG) circuitry, a test signal based on at least one of an output clock of clock divider circuitry or a data stream of signal generator circuitry;
generating, by the clock divider circuitry, a plurality of output clocks;
generating, by the signal generator circuitry, the data stream based on a mode of operation;
dividing, by the clock divider circuitry, an input clock by one or more counter values to generate the plurality of output clocks; and
modifying, by the signal generator circuitry, a register value based on at least one of the plurality of output clocks and the mode of operation to modify the data stream.

### Claim 16 (depends on 15)

The method of claim 15, further includes coupling one of the plurality of output clocks to an output of the EPG circuitry to set the test signal as one or more synchronous clock signals.

### Claim 17 (depends on 15)

The method of claim 15, further includes coupling at least a portion of the register value to an output of the EPG circuitry to set the test signal as a serial data stream.

### Claim 18 (depends on 15)

The method of claim 15, further includes coupling one of the plurality of output clocks to a first output of the EPG circuitry and a portion of the register value to a second output of the EPG circuitry to set the test signal as a clock signal and a configurable skewed serial data stream.

### Claim 19 (depends on 15)

The method of claim 15, further includes transforming the register value, by a controller, to generate one of a most significant bit first or a least significant bit first data stream.

### Claim 20 (depends on 15)

The method of claim 15, further includes counting a number of pulses of the input clock to generate the plurality of output clocks as a division of the input clock.

### Claim 21 (depends on 15)

The method of claim 15, further including determining the mode of operation to perform a transform operation to the register value, the mode of operation to be at least one of a bit bang mode, a shift right once mode, a shift right repeat mode, a rotate right once mode, a rotate right repeat mode, a shift left once mode, a shift left repeat mode, a rotate left once mode, or a rotate left repeat mode.