# US 12,119,819 B1 · Power-up switch-interconnect configuration > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,819 B1 - Document ID: US12119819B1 - Status: Granted - Kind: B1 - Application number: 18/078,033 - Filed: 2022-12-08 - Granted: 2024-10-15 - Earliest claimed: 2021-12-13 - Assignees: Flex Logix Technologies, Inc. - Applicants: Flex Logix Technologies, Inc. - Inventors: Robert I-Che Fu; Frederick A. Ware - Web page: https://patentgrep.com/patent/US12119819B1 ## CPC - H03K 19/1776: for memories - G11C 11/412: using field-effect transistors only - G11C 11/417: for memory cells of the field-effect type - H03K 19/17704: the logic functions being realised by the interconnection of rows and columns - H03K 19/17784: for supply voltage - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract In an integrated circuit component having a switch interconnect network and a configuration memory, a constituent multiplexer of the switch interconnect network includes a plurality of pass-gates having respective outputs coupled in common to a pass-gate output node, respective inputs that constitute respective signal inputs of the multiplexer, and control inputs coupled to receive respective pass-gate control signals having logic states according to configuration data stored within the configuration memory. Power-up control circuitry within the switch interconnect network drives the pass-gate output node of the multiplexer to a predetermined voltage level following power-up of the integrated circuit component and prior to execution of a programming operation in which one or more word-lines within the configuration memory are activated to store the configuration data within the configuration memory. ## Claims ### Claim 1 An integrated circuit component comprising: configuration memory; a first multiplexer within a switch interconnect network, the first multiplexer including a plurality of pass-gates having (i) respective outputs coupled in common to a pass-gate output node, (ii) respective inputs that constitute respective signal inputs of the first multiplexer, and (iii) control inputs coupled to receive respective pass-gate control signals from the configuration memory in accordance with configuration data stored within the configuration memory; and control circuitry to drive the pass-gate output node to a predetermined voltage level following power-up of the integrated circuit component and prior to execution of a programming operation in which one or more word-lines within the configuration memory are activated to store the configuration data within the configuration memory, the control circuitry to drive the pass-gate output node to the predetermined voltage level including a transistor coupled between one of the control inputs and a supply voltage node and circuitry to switch on the transistor. ### Claim 2 (depends on 1) The integrated circuit component of claim 1 wherein the transistor comprises an n-type metal-oxide-semiconductor transistor coupled between the one of the control inputs and a ground voltage node. ### Claim 3 (depends on 1) The integrated circuit component of claim 1 wherein, when switched on, the transistor coupled between the one of the control inputs and the supply voltage rail conductively couples an output of a storage cell within the configuration memory to the supply voltage rail. ### Claim 4 (depends on 3) The integrated circuit component of claim 3 wherein: after switching on the transistor coupled between the one of the control inputs and the supply voltage rail, the control circuitry switches off the transistor prior to execution of the programming operation; and the conductive coupling of the output of the storage cell within the configuration memory to the supply voltage rail via the transistor establishes a deterministic logic state within the storage cell that maintains signal assertion at the one of the control inputs such that a corresponding one of the pass-gates remains in a conducting state after the transistor coupled between the one of the control inputs and the supply voltage rail is switched off. ### Claim 5 (depends on 4) The integrated circuit component of claim 4 wherein: the storage cell comprises a bi-stable latch element that, as power is initially applied to the integrated circuit component, initializes arbitrarily in either of two logic states; and wherein the conductive coupling of the output of the storage cell within the configuration memory to the supply voltage rail establishes, as the deterministic logic state within the storage cell, a deterministic one of the two logic states. ### Claim 6 (depends on 4) The integrated circuit component of claim 4 wherein the storage cell comprises a bi-stable latch element having complementary output nodes to output a differential control signal to differential control inputs of a one of the pass-gates, and wherein the conductive coupling of the output of the storage cell to the supply voltage rail via the transistor comprises a conductive coupling of only one of the complementary output nodes to the supply voltage rail via the transistor. ### Claim 7 (depends on 6) The integrated circuit component of claim 6 wherein the bi-stable latch element comprises first and second inverters each having an output coupled to an input of the other, and wherein the conductive coupling of only one of the complementary output nodes to the supply voltage rail drives an input of the first inverter to a first one of the two logic states corresponding to a voltage level of the supply voltage rail such that (i) an output of the first inverter drives the input of the second inverter to a second one of the two logic states, and (ii) the first and second inverters are latched into the deterministic one of the two logic states within the storage cell. ### Claim 8 An integrated circuit component comprising: configuration memory; a first multiplexer within a switch interconnect network, the first multiplexer including a plurality of pass-gates having (i) respective outputs coupled in common to a pass-gate output node, (ii) respective inputs that constitute respective signal inputs of the first multiplexer, and (iii) control inputs coupled to receive respective pass-gate control signals from the configuration memory in accordance with configuration data stored within the configuration memory; and control circuitry to assert an override signal throughout a first interval to (i) switch on a transistor coupled between the pass-gate output node and a supply voltage rail, and (ii) enforce uniform voltage levels at the signal inputs of the first multiplexer, wherein the first interval commences following power-up of the integrated circuit component and prior to execution of a programming operation in which one or more word-lines within the configuration memory are activated to store the configuration data within the configuration memory. ### Claim 9 (depends on 8) The integrated circuit component of claim 8 wherein the supply voltage rail comprises a ground voltage rail such that the circuitry to switch on the transistor coupled between the pass-gate output node and the supply voltage rail comprises circuitry to pull the pass-gate output node down toward a ground voltage supply level. ### Claim 10 (depends on 8) The integrated circuit component of claim 8 wherein the supply voltage rail comprises a positive supply voltage rail such that the circuitry to switch on the transistor coupled between the pass-gate output node and the supply voltage rail comprises circuitry to pull the pass-gate output node up toward a positive supply voltage level. ### Claim 11 A method of operation within an integrated circuit component having a configuration memory and a first multiplexer within a switch interconnect network, the first multiplexer including a plurality of pass-gates having (i) respective outputs coupled in common to a pass-gate output node, (ii) respective inputs that constitute respective signal inputs of the first multiplexer, and (iii) control inputs coupled to receive respective pass-gate control signals from the configuration memory in accordance with configuration data stored within the configuration memory, the method comprising: after power-up of the integrated circuit component and prior to activating word-lines within the configuration memory to store the configuration data therein, switching on a transistor coupled between one of the control inputs and a supply voltage rail to drive the pass-gate output node to a predetermined voltage level; and activating one or more of the word-lines within the configuration memory to store the configuration data therein. ### Claim 12 (depends on 11) The method of claim 11 wherein switching on the transistor coupled between one of the control inputs and the supply voltage rail comprises switching on an n-type metal-oxide-semiconductor transistor coupled between the one of the control inputs and a ground voltage node. ### Claim 13 (depends on 11) The method of claim 11 wherein switching on the transistor coupled between the one of the control inputs and the supply voltage rail conductively couples an output of a storage cell within the configuration memory to the supply voltage rail. ### Claim 14 (depends on 13) The method of claim 13 further comprising switching off the transistor coupled between the one of the control inputs and the supply voltage rail prior to activating the one or more of the word-lines within the configuration memory to store the configuration data, wherein conductively coupling the output of the storage cell within the configuration memory to the supply voltage rail establishes a deterministic logic state within the storage cell that maintains signal assertion at the one of the control inputs such that a corresponding one of the pass-gates remains in a conducting state after switching off the transistor coupled between the one of the control inputs and the supply voltage rail. ### Claim 15 (depends on 14) The method of claim 14 wherein: the storage cell comprises a bi-stable latch element that, as power is initially applied to the integrated circuit component, initializes arbitrarily in either of two logic states; and wherein conductively coupling the output of the storage cell within the configuration memory to the supply voltage rail establishes, as the deterministic logic state within the storage cell, a deterministic one of the two logic states. ### Claim 16 (depends on 14) The method of claim 14 wherein the storage cell comprises a bi-stable latch element having complementary output nodes to output a differential control signal to differential control inputs of a one of the pass-gates, and wherein conductively coupling the output of the storage cell to the supply voltage rail comprises conductively coupling only one of the complementary output nodes to the supply voltage rail. ### Claim 17 (depends on 16) The method of claim 16 wherein the bi-stable latch element comprises first and second inverters each having an output coupled to an input of the other, and wherein conductively coupling only one of the complementary output nodes to the supply voltage rail drives an input of the first inverter to a first one of the two logic states corresponding to a voltage level of the supply voltage rail such that (i) an output of the first inverter drives the input of the second inverter to a second one of the two logic states, and (ii) the first and second inverters are latched into the deterministic one of the two logic states within the storage cell. ### Claim 18 A method of operation within an integrated circuit component having a configuration memory and a first multiplexer within a switch interconnect network, the first multiplexer including a plurality of pass-gates having (i) respective outputs coupled in common to a pass-gate output node, (ii) respective inputs that constitute respective signal inputs of the first multiplexer, and (iii) control inputs coupled to receive respective pass-gate control signals from the configuration memory in accordance with configuration data stored within the configuration memory, the method comprising: asserting an override signal throughout a first interval to (i) switch on a transistor coupled between the pass-gate output node and a supply voltage rail, and (ii) enforce uniform voltage levels at the signal inputs of the first multiplexer, wherein the first interval commences following power-up of the integrated circuit component and prior to execution of a programming operation in which one or more word-lines within the configuration memory are activated to store the configuration data within the configuration memory; and activating one or more of the word-lines within the configuration memory to store the configuration data therein. ### Claim 19 (depends on 18) The method of claim 18 wherein the first interval concludes after execution of the programming operation is completed. ### Claim 20 (depends on 18) The method of claim 18 wherein the supply voltage rail comprises a ground voltage rail such that switching on the transistor coupled between the pass-gate output node and the ground voltage rail pulls the pass-gate output node down toward a ground voltage supply level. ### Claim 21 (depends on 18) The method of claim 18 wherein the supply voltage rail comprises a positive supply voltage rail such that switching on the transistor coupled between the pass-gate output node and the positive supply voltage rail pulls the pass-gate output node up toward a positive supply voltage level.