# US 12,119,817 B2 · Gate driver circuits with independently tunable performance characteristics > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,817 B2 - Document ID: US12119817B2 - Status: Granted - Kind: B2 - Application number: 17/549,520 - Filed: 2021-12-13 - Published: 2023-06-15 - Granted: 2024-10-15 - Earliest claimed: 2021-12-13 - Assignees: ABB Schweiz AG - Applicants: ABB Schweiz AG - Inventors: Xiaoqing Song; Utkarsh Raheja; Pietro Cairoli; Sayan Acharya - Web page: https://patentgrep.com/patent/US12119817B2 ## CPC - H03K 17/163: {Soft switching} - H03K 17/6874: {in a symmetrical configuration} - H02H 3/087: for DC applications - H02H 7/22: for distribution gear, e.g. bus-bar systems; for switching devices {(detecting mechanical or electrical defects in gas-insulated switchgears H02B13/065)} - H03K 17/08122: {in field-effect transistor switches} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) ## Abstract A gate driver circuit is provided that includes a turn-on path, a turn-off path, and a fast discharge path. The turn-on path is couplable between a gate of a solid-state switch and a voltage turn-on signal (VGON) from a gate driver, where the turn-on path defines a turn-on time for the solid-state switch. The turn-off path is couplable between the gate and a voltage turn-off signal (VGOFF) from the gate driver, where the turn-off path defines a turn-off time for the solid-state switch. The fast discharge path is selectively couplable in parallel with the turn-off path during a portion of a gate-to-source voltage (VGS) transition for the solid-state switch, where the turn-off path in parallel with the fast discharge path defines a turn-off delay for the solid-state switch and each of the turn-on time, the turn-off time, and the turn-off delay are independently configurable. ## Claims ### Claim 1 A gate driver circuit, comprising: a turn-on circuit path couplable between a gate of a solid-state switch and a voltage turn-on signal (VGON) from a gate driver, wherein the turn-on circuit path defines a turn-on time for the solid-state switch; a turn-off circuit path couplable between the gate of the solid-state switch and a voltage turn-off signal (VGOFF) from the gate driver, wherein the turn-off circuit path defines a turn-off time for the solid-state switch; and a fast discharge circuit path selectively couplable in parallel with the turn-off circuit path during a portion of a gate-to-source voltage (VGS) transition for the solid-state switch, wherein the turn-off circuit path in parallel with the fast discharge circuit path defines a turn-off delay for the solid-state switch, wherein each of the turn-on time, the turn-off time, and the turn-off delay are independently configurable. ### Claim 2 (depends on 1) The gate driver circuit of claim 1, wherein: the portion of the VGS transition where the fast discharge circuit path is in parallel with the turn-off circuit path is between about VGON and about a threshold voltage VTH of the gate of the solid-state switch. ### Claim 3 (depends on 1) The gate driver circuit of claim 1, wherein: the turn-off circuit path defines the turn-off time based on a target maximum di/dt for a drain current of the solid-state switch. ### Claim 4 (depends on 1) The gate driver of claim 1, wherein: the fast discharge circuit path comprises: a first resistor having a first terminal coupled to VGOFF and a second terminal; a n-channel Field-Effect Transistor (FET) having a drain coupled to the gate of the solid-state switch, a source coupled to the second terminal of the first resistor, and a gate; a Zener diode having a cathode coupled to the drain of the n-channel FET and an anode coupled to the gate of the n-channel FET; and a second resistor having a third terminal coupled to the gate of the n-channel FET and a fourth terminal coupled to the source of the n-channel FET. ### Claim 5 (depends on 4) The gate driver circuit of claim 4, wherein: the turn-off circuit path comprises a third resistor having a fifth terminal coupled to VGOFF and a sixth terminal coupled to the gate of the solid-state switch. ### Claim 6 (depends on 4) The gate driver circuit of claim 4, wherein: the n-channel FET conducts when |VGOFF|+VGS−VTOG>VZ, where VTOG is a threshold voltage for the n-channel FET and VZ is a Zener breakdown voltage for the Zener diode. ### Claim 7 (depends on 6) The gate driver circuit of claim 6, wherein: VZ is equal to about |VGOFF|+VGSP, where VGSP is a gate plateau voltage of the solid-state switch. ### Claim 8 (depends on 1) The gate driver circuit of claim 1, wherein: the fast discharge circuit path comprises: a first resistor having a first terminal coupled to VGOFF and a second terminal; a p-channel Field-Effect Transistor (FET) having a source coupled to the gate of the solid-state switch, a drain coupled to the second terminal of the first resistor, and a gate; a second resistor having a third terminal coupled to the source of the p-channel FET and a fourth terminal coupled to the gate of the p-channel FET; a third resistor having a fifth terminal coupled to the gate of the p-channel FET and a sixth terminal; and a Zener diode having a cathode coupled to the sixth terminal of the third resistor and an anode coupled to a source of the solid-state switch. ### Claim 9 (depends on 8) The gate driver circuit of claim 8, wherein: the p-channel FET conducts when VGS>VZ+|VTOG|, where VTOG is a threshold voltage for the p-channel FET and VZ is a Zener breakdown voltage for the Zener diode. ### Claim 10 (depends on 8) The gate driver circuit of claim 8, wherein: the turn-off circuit path comprises a fourth resistor having a seventh terminal coupled to VGOFF and a eighth terminal coupled to the gate of the solid-state switch. ### Claim 11 A solid-state circuit breaker, comprising: a first output terminal; a second output terminal; at least one gate driver configured to generate a turn-on signal VGON and a turn-off signal VGOFF; a pair of anti-series solid-state switches selectively coupling the first output terminal with the second output terminal; and a gate driver circuit coupled to the at least one gate driver and a first solid-state switch of the pair of anti-series solid-state switches, the gate driver circuit comprising: a turn-on circuit path coupled between a gate of the first solid-state switch and VGON, wherein the turn-on circuit path defines a turn-on time for the first solid-state switch; a turn-off circuit path coupled between the gate of the first solid-state switch and VGOFF, wherein the turn-off circuit path defines a turn-off time for the first solid-state switch; and a fast discharge circuit path selectively coupled in parallel with the turn-off circuit path during a portion of a gate-to-source voltage (VGS) transition for the first solid-state switch, wherein the turn-off circuit path in parallel with the fast discharge circuit path defines a turn-off delay for the first solid-state switch, wherein each of the turn-on time, the turn-off time, and the turn-off delay are independently configurable. ### Claim 12 (depends on 11) The solid-state circuit breaker of claim 11, wherein: the portion of the VGS transition where the fast discharge circuit path is in parallel with the turn-off circuit path is between about VGON and about a threshold voltage VTH of the gate of the first solid-state switch. ### Claim 13 (depends on 11) The solid-state circuit breaker of claim 11, wherein: the turn-off circuit path defines the turn-off time based on a target maximum di/dt for a fault current for the solid-state circuit breaker. ### Claim 14 (depends on 11) The solid-state circuit breaker of claim 11, wherein: the fast discharge circuit path comprises: a first resistor having a first terminal coupled to VGOFF and a second terminal; a n-channel Field-Effect Transistor (FET) having a drain coupled to the gate of the first solid-state switch, a source coupled to the second terminal of the first resistor, and a gate; a Zener diode having a cathode coupled to the drain of the n-channel FET and an anode coupled to the gate of the n-channel FET; and a second resistor having a third terminal coupled to the gate of the n-channel FET and a fourth terminal coupled to the source of the n-channel FET. ### Claim 15 (depends on 14) The solid-state circuit breaker of claim 14, wherein: the turn-off circuit path comprises a third resistor having a fifth terminal coupled to VGOFF and a sixth terminal coupled to the gate of the first solid-state switch. ### Claim 16 (depends on 15) The solid-state circuit breaker of claim 15, wherein: the n-channel FET conducts when |VGOFF|+VGS−VTOG>VZ, where VTOG is a threshold voltage for the n-channel FET and VZ is a Zener breakdown voltage for the Zener diode. ### Claim 17 (depends on 16) The solid-state circuit breaker of claim 16, wherein: VZ is equal to about |VGOFF|+VGSP, where VGSP is a gate plateau voltage of the first solid-state switch. ### Claim 18 (depends on 11) The solid-state circuit breaker of claim 11, wherein: the fast discharge circuit path comprises: a first resistor having a first terminal coupled to VGOFF and a second terminal; a p-channel Field-Effect Transistor (FET) having a source coupled to the gate of the first solid-state switch, a drain coupled to the second terminal of the first resistor, and a gate; a second resistor having a third terminal coupled to source of the p-channel FET and a fourth terminal coupled to the gate of the p-channel FET; a third resistor having a fifth terminal coupled to the gate of the p-channel FET and a sixth terminal; and a Zener diode having a cathode coupled to the sixth terminal of the third resistor and an anode coupled to a source of the first solid-state switch. ### Claim 19 (depends on 18) The solid-state circuit breaker of claim 18, wherein: the p-channel FET conducts when VGS>VZ+|VTOG|, where VTOG is a threshold voltage for the FET and VZ is a Zener breakdown voltage for the Zener diode. ### Claim 20 An apparatus comprising: a gate driver configured to generate a turn-off signal VGOFF; a solid-state switch including a gate, a drain, and a source; a turn-off circuit path coupled between the gate of the solid-state switch and VGOFF; and a fast discharge circuit path comprising one of: a first circuit comprising a first resistor having a first terminal coupled to VGOFF and a second terminal, a n-channel Field-Effect Transistor (FET) having a drain coupled to the gate of the solid-state switch, a source coupled to the second terminal of the first resistor, and a gate, a first Zener diode having a cathode coupled to the drain of the n-channel FET and an anode coupled to the gate of the n-channel FET, and a second resistor having a third terminal coupled to the gate of the n-channel FET and a fourth terminal coupled to the source of the n-channel FET; and a second circuit comprising a third resistor having a fifth terminal coupled to VGOFF and a sixth terminal, a p-channel FET having a source coupled to the gate of the solid-state switch, a drain coupled to the sixth terminal of the third resistor, and a gate, a fourth resistor having a seventh terminal coupled to the source of the p-channel FET and a eighth terminal coupled to the gate of the p-channel FET, a fifth resistor having a ninth terminal coupled to the gate of the p-channel FET and a tenth terminal, and a second Zener diode having a cathode coupled to the tenth terminal of the fifth resistor and an anode coupled to a source of the solid-state switch.