# US 12,119,816 B2 · Semiconductor device and semiconductor device control method

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- Number: US 12,119,816 B2
- Document ID: US12119816B2
- Status: Granted
- Kind: B2
- Application number: 17/953,023
- Filed: 2022-09-26
- Published: 2023-04-06
- Granted: 2024-10-15
- Earliest claimed: 2021-09-30
- Assignees: LAPIS Technology Co., Ltd.
- Applicants: LAPIS Technology Co., Ltd.
- Inventors: Keisuke Kiyomizu
- Web page: https://patentgrep.com/patent/US12119816B2

## CPC

- H03K 3/356017: {using additional transistors in the input circuit (H03K3/356104, H03K3/3562 take precedence)}
- H03K 17/6872: {using complementary field-effect transistors}
- H03K 3/037: Bistable circuits
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A semiconductor device, includes: a first first-conductivity-type transistor supplied with a first power source voltage and controlled by an output signal of a first input inverter; a second first-conductivity-type transistor supplied with the first power source voltage and controlled by an output signal of a second input inverter that inverts an output signal of the first input inverter; a first and a second second-conductivity-type transistor supplied with a second power source voltage; and a third and a fourth first-conductivity-type transistor that are connected in parallel either between the first first-conductivity-type transistor and the first second-conductivity-type transistor or between the second first-conductivity-type transistor and the second second-conductivity-type transistor, and that are configured to isolate either a first node connected to the first first-conductivity-type transistor or a second node connected to the second first-conductivity-type transistor from the second power source voltage in accordance with the first power source voltage.

## Claims

### Claim 1

A semiconductor device that operates at a first power source voltage and at a second power source voltage higher than the first power source voltage and that comprises:
a first first-conductivity-type transistor supplied with the first power source voltage and controlled by an output signal of a first input inverter that inverts an input signal;
a second first-conductivity-type transistor supplied with the first power source voltage and controlled by an output signal of a second input inverter that inverts the output signal of the first input inverter;
a first second-conductivity-type transistor supplied with the second power source voltage;
a second second-conductivity-type transistor supplied with the second power source voltage; and
a third first-conductivity-type transistor and a fourth first-conductivity-type transistor that are connected in parallel either between the first first-conductivity-type transistor and the first second-conductivity-type transistor or between the second first-conductivity-type transistor and the second second-conductivity-type transistor, and that are configured to isolate either a first node connected to the first first-conductivity-type transistor or a second node connected to the second first-conductivity-type transistor from the second power source voltage in accordance with the first power source voltage;
wherein:
the output signal of the first input inverter is supplied to a gate of the third first-conductivity-type transistor; and
the output signal of the second input inverter is supplied to a gate of the fourth first-conductivity-type transistor.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the third first-conductivity-type transistor and the fourth first-conductivity-type transistor isolate the first node or the second node from the second power source voltage, in cases in which the first power source voltage is lower than a specific voltage.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising:
a third second-conductivity-type transistor connected between the first first-conductivity-type transistor and the first second-conductivity-type transistor, with the third second-conductivity-type transistor combining with the first first-conductivity-type transistor to configure a first inverter and being controlled by the output signal of the first input inverter; and
a fourth second-conductivity-type transistor connected between the second first-conductivity-type transistor and the second second-conductivity-type transistor, with the fourth second-conductivity-type transistor combining with the second first-conductivity-type transistor to configure a second inverter and being controlled by the output signal of the second input inverter, wherein:
the third first-conductivity-type transistor and the fourth first-conductivity-type transistor are connected in parallel either between the first first-conductivity-type transistor and the third second-conductivity-type transistor or between the second first-conductivity-type transistor and the fourth second-conductivity-type transistor.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein:
the second node is connected to a gate of the first second-conductivity-type transistor; and
the first node is connected to a gate of the second second-conductivity-type transistor.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein:
the first node is connected to a drain of the first first-conductivity-type transistor; and
the second node is connected to a drain of the second first-conductivity-type transistor.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein:
the first first-conductivity-type transistor, the second first-conductivity-type transistor, the third first-conductivity-type transistor, and the fourth first-conductivity-type transistor each comprise an NMOS transistor; and
the first second-conductivity-type transistor and the second second-conductivity-type transistor each comprise a PMOS transistor.