# US 12,119,814 B2 · Gate resistive ladder bypass for RF FET switch stack > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,814 B2 - Document ID: US12119814B2 - Status: Granted - Kind: B2 - Application number: 18/183,806 - Filed: 2023-03-14 - Published: 2023-09-07 - Granted: 2024-10-15 - Earliest claimed: 2021-10-01 - Assignees: pSemi Corporation - Applicants: pSemi Corporation - Inventors: Ravindranath D. Shrivastava; Alper Genc - Web page: https://patentgrep.com/patent/US12119814B2 ## CPC - H03K 17/102: {in field-effect transistor switches} - H03K 17/687: the devices being field-effect transistors - H03K 17/04123: {in field-effect transistor switches} - H03K 17/063: {in field-effect transistor switches} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches. ## Claims ### Claim 1 A FET switch stack comprising: a stacked arrangement of FET switches; a gate resistor network comprising one or more ladder resistors connected to gate terminals of the FET switches; one or more common gate resistors connected to the gate resistor network; and a gate resistor bypass arrangement comprising a first set of bypass switches connected across corresponding common gate resistors and a second set of bypass switches connected across corresponding ladder resistors, wherein each bypass switch in the first set of bypass switches comprises an nMOS and pMOS transistor pair connected in series and each bypass switch in the second set of bypass switches comprises an nMOS and pMOS transistor pair connected in series. ### Claim 2 (depends on 1) The FET switch stack of claim 1, wherein the gate resistor network and the one or more common gate resistors are configured to feed a gate control voltage to the gate terminals of the FET switches. ### Claim 3 (depends on 2) The FET switch stack of claim 2, wherein in a transition state of the stacked arrangement of FET switches, the gate resistor bypass arrangement is configured to bypass the one or more common gate resistors and the one or more ladder resistors. ### Claim 4 (depends on 3) The FET switch stack of claim 3, wherein in a steady state of the stacked arrangement of FET switches, the gate resistor bypass arrangement is configured not to bypass the one or more common gate resistors and the one or more ladder resistors. ### Claim 5 (depends on 3) The FET switch stack of claim 3, wherein the first set of bypass switches and the second set of bypass switches are in an ON state in the transition state. ### Claim 6 (depends on 4) The FET switch stack of claim 4, wherein the first set of bypass switches and the second set of bypass switches are in an OFF state in the steady state. ### Claim 7 (depends on 5) The FET switch stack of claim 5, wherein when the first set of bypass switches and the second set of bypass switches are in the OFF state, one of the nMOS transistor and the pMOS transistor of each transistor pair is in an OFF state and the other of the nMOS transistor and the pMOS transistor of each transistor pair is in an ON state. ### Claim 8 (depends on 1) The FET switch stack of claim 1, wherein the one or more ladder resistors comprise rail resistors and rung resistors. ### Claim 9 (depends on 8) The FET switch stack of claim 8, wherein the gate resistor bypass arrangement is configured to bypass the rail resistors only, the rung resistors only, or both the rail resistors and the rung resistors. ### Claim 10 (depends on 8) The FET switch stack of claim 8, wherein the gate resistor bypass arrangement is configured to bypass a first portion of the rail resistors and not bypass a remaining portion of the rail resistors. ### Claim 11 (depends on 1) The FET switch stack of claim 1, wherein the one or more ladder resistors comprise rail resistors only, the gate resistor bypass arrangement being configured to bypass the rail resistors. ### Claim 12 (depends on 1) The FET switch stack of claim 1, wherein the one or more ladder resistors comprise rung resistors only, and the gate resistor bypass arrangement is configured to bypass the rung resistors. ### Claim 13 (depends on 1) The FET switch stack of claim 1, wherein the first set of bypass switches comprises a number of switches that is a function of an internal voltage of the stacked arrangement of FET switches in an ON steady state. ### Claim 14 (depends on 1) The FET switch stack of claim 1 wherein the first set of bypass switches comprises a number of switches that is a function of an internal voltage of the stacked arrangement of FET switches in an OFF steady state. ### Claim 15 (depends on 1) The FET switch stack of claim 1, wherein the first set of bypass switches connected across the one or more common gate resistors are included in a single common gate resistors bypass feed. ### Claim 16 (depends on 1) The FET switch stack of claim 1, wherein the first set of bypass switches connected across the one or more common gate resistors are included in two separate common gate resistors bypass feeds, a first subset of the first set of bypass switches being connected with a first subset of the second set of bypass switches, and a second separate subset of the first set of bypass switches being connected with a second separate subset of the second set of bypass switches. ### Claim 17 (depends on 16) The FET switch stack of claim 16, wherein the gate resistor bypass arrangement is configured to bypass a first portion of the rail resistors and not to bypass a remaining portion of the rail resistors. ### Claim 18 (depends on 1) A receiver switch comprising the FET switch stack of claim 1. ### Claim 19 A FET switch stack comprising: a stacked arrangement of FET switches; a gate resistor network comprising ladder resistors connected to gate terminals of the FET switches; one or more common gate resistors connected to the gate resistor network; and a gate resistor bypass arrangement comprising a first set of bypass switches connected across corresponding common gate resistors and a second set of bypass switches connected across corresponding ladder resistors, wherein the gate resistor bypass arrangement is configured to bypass a first portion of the ladder resistors and not bypass a remaining portion of the ladder resistors.