# US 12,119,811 B2 · Gate driver output protection circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,811 B2 - Document ID: US12119811B2 - Status: Granted - Kind: B2 - Application number: 18/126,923 - Filed: 2023-03-27 - Published: 2023-09-28 - Granted: 2024-10-15 - Earliest claimed: 2021-04-28 - Assignees: Skyworks Solutions, Inc. - Applicants: Skyworks Solutions, Inc. - Inventors: Péter Onódy; Tamás Marozsák; Michael R. May; Fernando Naim Lavalle Aviles; Patrick De Bakker - Web page: https://patentgrep.com/patent/US12119811B2 ## CPC - H03K 17/0828: {in composite switches} - H03K 17/145: {in field-effect transistor switches} - H03K 17/18: Modifications for indicating state of switch - H03K 17/284: in field effect transistor switches - H03K 2017/0806: {against excessive temperature} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A method for protecting a system including a driver integrated circuit includes receiving a driver input signal. The method includes driving an output signal externally to the driver integrated circuit. The output signal is driven based on the driver input signal and an indication of a delay between receipt of an edge of the driver input signal and arrival of a corresponding edge of the output signal at an output node coupled to a terminal of the driver integrated circuit. ## Claims ### Claim 1 A method for protecting a system including a driver integrated circuit, the method comprising: receiving a driver input signal; generating a first indication of whether a rising edge of the driver input signal is delayed in an output signal at an output node of the driver integrated circuit coupled to a terminal of the driver integrated circuit; generating a second indication of whether a falling edge of the driver input signal is delayed in the output signal at the output node; and generating an error signal based on the first indication and the second indication; and driving the output signal externally to the driver integrated circuit, the output signal being driven based on the driver input signal and the error signal. ### Claim 2 (depends on 1) The method of claim 1 further comprising generating a counter value indicative of an amount of delay, and wherein generating the error signal is based on the counter value. ### Claim 3 (depends on 2) The method of claim 2 wherein generating the counter value includes incrementing the counter value during delay intervals and decrementing the counter value during non-delay intervals. ### Claim 4 (depends on 1) The method of claim 1 wherein generating the error signal is based on an average of delay over time. ### Claim 5 (depends on 1) The method of claim 1 wherein driving the output signal includes configuring an output driver to enter a safer output state for a predetermined interval in response to detecting an error condition based on the first indication. ### Claim 6 (depends on 5) The method of claim 5 wherein driving the output signal further includes transitioning from the safer output state to a normal state in response to expiration of the predetermined interval in the safer output state. ### Claim 7 (depends on 5) The method of claim 5 wherein the output driver is configured to transition to the safer output state from a second safer output state and in response to a second expiration of a second predetermined interval in the second safer output state, and driving the output signal further includes transitioning to the second safer output state from a normal output state. ### Claim 8 (depends on 5) The method of claim 5 wherein in the safer output state, an output device of the output driver is configured in a strong pull-down configuration or a weak pull-down configuration, the output driver being configured in the weak pull-down configuration from the strong pull-down configuration after a predetermined period of time. ### Claim 9 (depends on 1) The method of claim 1 wherein the output signal is driven further based on a third indication of a sensed temperature of the driver integrated circuit, and the method further comprises: generating the third indication based on the sensed temperature of a die of the driver integrated circuit; and configuring an output driver to enter a safer output state in response to the third indication exceeding a predetermined threshold. ### Claim 10 An integrated circuit configured to control a drive device, the integrated circuit comprising: a driver circuit configured to drive an output signal to a terminal of the integrated circuit, the output signal being driven based on a driver input signal and an error signal; and a logic circuit configured to generate a first indication of whether a rising edge of the driver input signal is delayed in the output signal, to generate a second indication of whether a falling edge of the driver input signal is delayed in the output signal, and to generate an error signal based on the first indication and the second indication. ### Claim 11 (depends on 10) The integrated circuit of claim 10 wherein the logic circuit includes a counter circuit configured to increment a counter value corresponding to an amount of delay, and generation of the error signal is based on the counter value. ### Claim 12 (depends on 11) The integrated circuit of claim 11 wherein the counter circuit is further configured to increment the counter value during delay intervals delay intervals and decrement the counter value during non-delay intervals. ### Claim 13 (depends on 10) The integrated circuit of claim 10 wherein generation of the error signal is based on an average of delay over time. ### Claim 14 (depends on 10) The integrated circuit of claim 10 wherein the logic circuit is further configured to drive the output signal by configuring an output driver to enter a safer output state for a predetermined interval in response to detecting an error condition based on the first indication. ### Claim 15 (depends on 14) The integrated circuit of claim 14 wherein the logic circuit is further configured to transition the output driver from the safer output state to a normal state in response to expiration of a predetermined interval in the safer output state and no other error condition being detected. ### Claim 16 (depends on 14) The integrated circuit of claim 14 wherein the logic circuit is further configured to transition the output driver to the safer output state from a second safer output state and in response to a second expiration of a second predetermined interval in the second safer output state, and driving the output signal further includes transitioning to the second safer output state from a normal output state. ### Claim 17 (depends on 14) The integrated circuit of claim 14 wherein in the safer output state, an output device of the output driver is configured in a strong pull-down configuration or a weak pull-down configuration, the output driver being configured in the weak pull-down configuration from the strong pull-down configuration after a predetermined period of time. ### Claim 18 (depends on 10) The integrated circuit of claim 10 further comprising a temperature sensor configured to sense a temperature of the integrated circuit, the output signal being driven further based on a second indication, and the logic circuit being configured to generate the second indication based on a sensed temperature of the integrated circuit and to cause an output driver to enter a safer output state in response to the second indication exceeding a predetermined threshold. ### Claim 19 An electronics system comprising: a gate driver integrated circuit including a driver circuit configured to drive an output signal to a terminal of the gate driver integrated circuit, the output signal being driven based on a driver input signal and an error signal, and a logic circuit configured to generate a first indication of whether a rising edge of the driver input signal is delayed in the output signal, to generate a second indication of whether a falling edge of the driver input signal is delayed in the output signal, and to generate an error signal based on the first indication and the second indication; and a drive transistor coupled to the terminal of the gate driver integrated circuit to receive the output signal. ### Claim 20 (depends on 19) The electronics system of claim 19 further comprising an isolation barrier and isolation communications channel, the driver input signal received from the isolation communications channel.