# US 12,119,810 B2 · Gate driver system for detecting a short circuit condition > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,810 B2 - Document ID: US12119810B2 - Status: Granted - Kind: B2 - Application number: 17/933,615 - Filed: 2022-09-20 - Published: 2024-03-21 - Granted: 2024-10-15 - Earliest claimed: 2022-09-20 - Assignees: Infineon Technologies Austria AG - Applicants: Infineon Technologies Austria AG - Inventors: Yuqiang Qiu; Bin Tian - Web page: https://patentgrep.com/patent/US12119810B2 ## CPC - H03K 17/08104: {in field-effect transistor switches (H03K17/0812, H03K17/0814 take precedence)} - G01R 31/52: Testing for short-circuits, leakage current or ground faults - H02J 7/90: Regulation of charging or discharging current or voltage - H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters - H02M 1/32: Means for protecting converters other than automatic disconnection - H02M 7/5387: in a bridge configuration - H02P 27/08: with pulse width modulation - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H02J: ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H02P: CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS ## Abstract A driver system includes a first half-bridge that generates a first load current at a first output node, a second half-bridge that generates a second load current at a second output node, a first voltage charging device coupled to the first output node, and a second voltage charging device coupled to the second output node. A method of detecting a short circuit condition in the driver system includes detecting a first charging time at which a first charging voltage of the first voltage charging device is charged to a first threshold voltage; detecting a second charging time at which a second charging voltage of the second voltage charging device is charged to a second threshold voltage; and detecting the short circuit condition on a condition that a time difference between the first charging time and the second charging time is less than a time difference threshold. ## Claims ### Claim 1 A driver system configured to drive a motor, the driver system comprising: a first half-bridge circuit comprising a first high-side transistor and a first low-side transistor coupled at a first output node, wherein the first high-side transistor and the first low-side transistor are configured to cooperatively generate a first load current at the first output node for driving the motor; a second half-bridge circuit comprising a second high-side transistor and a second low-side transistor coupled at a second output node, wherein the second high-side transistor and the second low-side transistor are configured to cooperatively generate a second load current at the second output node for driving the motor; a first voltage charging device coupled to a first power supply and to the first output node; a second voltage charging device coupled to a second power supply and to the second output node; and a diagnostic circuit configured to monitor a first charging voltage of the first voltage charging device and a second charging voltage of the second voltage charging device, detect a first charging time at which the first charging voltage is charged to a first threshold voltage, detect a second charging time at which the second charging voltage is charged to a second threshold voltage, and detect a short circuit condition on a condition that a time difference between the first charging time and the second charging time is less than a time difference threshold. ### Claim 2 (depends on 1) The driver system of claim 1, wherein the diagnostic circuit is configured to detect a normal operating condition on a condition that the time difference between the first charging time and the second charging time is equal to or greater than the time difference threshold. ### Claim 3 (depends on 1) The driver system of claim 1, wherein the diagnostic circuit is configured to detect the short circuit condition on a condition that the second charging time occurs at a time delay relative to the first charging time that is less than the time difference threshold. ### Claim 4 (depends on 3) The driver system of claim 3, wherein the diagnostic circuit is configured to detect a normal operating condition on a condition that the second charging time occurs at a time delay relative to the first charging time that is equal to or greater than the time difference threshold. ### Claim 5 (depends on 1) The driver system of claim 1, further comprising: a driver circuit configured to generate control signals to drive the first high-side transistor, the first low-side transistor, the second high-side transistor, and the second low-side transistor between respective switching states, including at least an on state and an off state, wherein while the diagnostic circuit monitors the first charging voltage of the first voltage charging device and the second charging voltage of the second voltage charging device, the driver circuit is configured to maintain the first high-side transistor, the second high-side transistor, and the second low-side transistor in the off state and drive the first low-side transistor between the on state and the off state. ### Claim 6 (depends on 5) The driver system of claim 5, wherein: wherein while the diagnostic circuit monitors the first charging voltage of the first voltage charging device and the second charging voltage of the second voltage charging device, the driver circuit is configured to generate one of the control signals as a varying drive signal and provide the varying drive signal to a control terminal of the first low-side transistor to drive the first low-side transistor between the on state and the off state. ### Claim 7 (depends on 6) The driver system of claim 6, wherein the varying drive signal is a pulse-width modulation (PWM) drive signal. ### Claim 8 (depends on 6) The driver system of claim 6, wherein the driver circuit is configured to start the varying drive signal at a start time, and wherein a charging of the first voltage charging device and a charging of the second voltage charging device start at the start time. ### Claim 9 (depends on 8) The driver system of claim 8, wherein the diagnostic circuit is configured to determine the first charging time as a first duration from the start time to a first subsequent time at which the first charging voltage is charged to the first threshold voltage and determine the second charging time as a second duration from the start time to a second subsequent time at which the second charging voltage is charged to the second threshold voltage. ### Claim 10 (depends on 5) The driver system of claim 5, wherein the driver circuit comprises: a first driver configured to generate the control signals to drive the first high-side transistor and the first low-side transistor between respective switching states; and a second driver configured to generate the control signals to drive the second high-side transistor and the second low-side transistor between respective switching states. ### Claim 11 (depends on 5) The driver system of claim 5, wherein, while the first high-side transistor, the second high-side transistor, and the second low-side transistor are in the off state and while the first low-side transistor is driven between the on state and the off state, a first current is configured to flow from the first voltage charging device through the first output node, and through the first low-side transistor and a second current is configured to flow from the second voltage charging device, through the second output node, and through the first low-side transistor, wherein under a normal operating condition, the second current is configured to flow from the second output node to the first low-side transistor through motor windings of the motor, and wherein under a fault condition during which the short circuit condition is present, the second current is configured to flow from the second output node to the first low-side transistor via a short circuit. ### Claim 12 (depends on 1) The driver system of claim 1, further comprising: a driver circuit configured to generate control signals to drive the first high-side transistor, the first low-side transistor, the second high-side transistor, and the second low-side transistor between respective switching states, including at least an on state and an off state, wherein while the diagnostic circuit monitors the first charging voltage of the first voltage charging device and the second charging voltage of the second voltage charging device, the driver circuit is configured to maintain the first high-side transistor, the second high-side transistor, and the second low-side transistor in an off state and drive the first low-side transistor between the on state and the off state, wherein the diagnostic circuit is configured to detect a normal operating condition on a condition that the time difference between the first charging time and the second charging time is equal to or greater than the time difference threshold, and wherein, on a condition that the diagnostic circuit detects the normal operating condition, the diagnostic circuit is configured to enable switching of the first high-side transistor and the second high-side transistor between respective switching states. ### Claim 13 (depends on 1) The driver system of claim 1, wherein, on a condition that the diagnostic circuit detects the short circuit condition, the diagnostic circuit is configured to disable switching of the first high-side transistor and the second high-side transistor between respective switching states. ### Claim 14 (depends on 1) The driver system of claim 1, wherein the diagnostic circuit includes a first comparator circuit configured to compare the first charging voltage to the first threshold voltage and generate a first comparison result and a second comparator circuit configured to compare the second charging voltage to the second threshold voltage and generate a second comparison result, wherein the diagnostic circuit detects the first charging time based on the first comparison result and detects the second charging time based on the second comparison result. ### Claim 15 (depends on 14) The driver system of claim 14, where the diagnostic circuit is configured to calculate the time difference based on the first charging time and the second charging time, compare the time difference to the time difference threshold to generate a third comparison result, and detect the short circuit condition based on the third comparison result. ### Claim 16 (depends on 1) The driver system of claim 1, further comprising: a driver circuit configured to generate control signals to drive the first high-side transistor, the first low-side transistor, the second high-side transistor, and the second low-side transistor between respective switching states, including at least an on state and an off state, wherein the driver circuit is configured to initiate a charging of the first voltage charging device and a charging of the second voltage charging device at a start time, wherein the diagnostic circuit is configured to detect the short circuit condition on a condition that the diagnostic circuit detects both the first charging time and the second charging time within a predetermined time period extending from the start time. ### Claim 17 (depends on 16) The driver system of claim 16, wherein the diagnostic circuit is configured to detect a normal operating condition on a condition that the diagnostic circuit detects that the second charging time occurs at time equal to or later than the predetermined time period extending from the start time. ### Claim 18 (depends on 1) The driver system of claim 1, wherein the first power supply and the second power supply are a same power supply. ### Claim 19 (depends on 1) The driver system of claim 1, wherein the first voltage charging device is a first bootstrap capacitor and the second voltage charging device is a second bootstrap capacitor. ### Claim 20 (depends on 19) The driver system of claim 19, wherein the first charging voltage is representative of a voltage across the first bootstrap capacitor and the second charging voltage is representative of a voltage across the second bootstrap capacitor. ### Claim 21 (depends on 19) The driver system of claim 19, further comprising: a first driver configured to drive the first high-side transistor and the first low-side transistor between respective switching states; and a second driver configured to drive the second high-side transistor and the second low-side transistor between respective switching states, wherein the first charging voltage is a first high-side floating supply voltage of the first driver and the second charging voltage is a second high-side floating supply voltage of the second driver. ### Claim 22 (depends on 1) The driver system of claim 1, further comprising: a third half-bridge circuit comprising a third high-side transistor and a third low-side transistor coupled at a third output node, wherein the third high-side transistor and the third low-side transistor are configured to cooperatively generate a third load current at the third output node for driving the motor; and a third voltage charging device coupled to a third power supply and to the third output node, wherein the diagnostic circuit is configured to monitor the first charging voltage of the first voltage charging device, the second charging voltage of the second voltage charging device, and a third charging voltage of the third voltage charging device, detect the first charging time at which the first charging voltage is charged to the first threshold voltage, detect the second charging time at which the second charging voltage is charged to the second threshold voltage, detect the third charging time at which the third charging voltage is charged to a third threshold voltage, and detect the short circuit condition on a condition that a first time difference between the first charging time and the second charging time is less than the time difference threshold or on a condition that a second time difference between the first charging time and the third charging time is less than the time difference threshold. ### Claim 23 (depends on 22) The driver system of claim 22, wherein the diagnostic circuit is configured to detect a normal operating condition on a condition that the first time difference and the second time difference are both equal to or greater than the time difference threshold. ### Claim 24 (depends on 23) The driver system of claim 23, further comprising: a driver circuit configured to generate control signals to drive the first high-side transistor, the first low-side transistor, the second high-side transistor, the second low-side transistor, the third high-side transistor, and the third low-side transistor between respective switching states, including at least an on state and an off state, wherein while the diagnostic circuit monitors the first charging voltage of the first voltage charging device and the second charging voltage of the second voltage charging device, the driver circuit is configured to maintain the first high-side transistor, the second high-side transistor, the third high-side transistor, the second low-side transistor, and the third low-side transistor in an off state and drive the first low-side transistor between the on state and the off state, and wherein, on a condition that the diagnostic circuit detects the normal operating condition, the diagnostic circuit is configured to enable switching of the first high-side transistor, the second high-side transistor, and the third high-side transistor between respective switching states. ### Claim 25 (depends on 24) The driver system of claim 24, wherein, on a condition that the diagnostic circuit detects the short circuit condition, the diagnostic circuit is configured to disable switching of the first high-side transistor, the second high-side transistor, and the third high-side transistor between respective switching states. ### Claim 26 (depends on 22) The driver system of claim 22, wherein the first power supply, the second power supply, and the third power supply are a same power supply. ### Claim 27 (depends on 22) The driver system of claim 22, wherein, on a condition that the diagnostic circuit detects the short circuit condition, the diagnostic circuit is configured to generate a short circuit fault signal that indicates a fault location of the short circuit condition. ### Claim 28 A method of detecting a short circuit condition in a driver system comprising a first half-bridge circuit configured to generate a first load current at a first output node, a second half-bridge circuit configured to generate a second load current at a second output node, a first voltage charging device coupled to a first power supply and to the first output node, and a second voltage charging device coupled to a second power supply and to the second output node, the method comprising: monitoring a first charging voltage of the first voltage charging device and a second charging voltage of the second voltage charging device; detecting a first charging time at which the first charging voltage is charged to a first threshold voltage; detecting a second charging time at which the second charging voltage is charged to a second threshold voltage; and detecting the short circuit condition on a condition that a time difference between the first charging time and the second charging time is less than a time difference threshold. ### Claim 29 (depends on 28) The method of claim 28, further comprising: detecting a normal operating condition on a condition that the time difference between the first charging time and the second charging time is equal to or greater than the time difference threshold.