# US 12,119,795 B2 · Amplifier circuit and display apparatus having the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,795 B2 - Document ID: US12119795B2 - Status: Granted - Kind: B2 - Application number: 18/501,389 - Filed: 2023-11-03 - Published: 2024-08-01 - Granted: 2024-10-15 - Earliest claimed: 2023-01-30 - Assignees: LG Display Co., Ltd. - Applicants: LG Display Co., Ltd. - Inventors: HongJu Lee; Hyunwoo Kim; Beom-Jin Kim - Web page: https://patentgrep.com/patent/US12119795B2 ## CPC - H03F 3/211: {using a combination of several amplifiers (H03F3/60 takes precedence)} - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3275: Details of drivers for data electrodes - G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit - G09G 2320/0252: Improving the response speed - G09G 2330/021: Power management, e.g. power saving - H03F 2200/366: Multiple MOSFETs are coupled in parallel - H03F 2200/87: the cross coupling circuit being realised only by MOSFETs - H03F: AMPLIFIERS - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract Disclosed is an amplifier circuit comprising a first stage having first and second input terminals, a second stage configured to amplify a voltage supplied from the first stage and including a pull-up node and a pull-down node, a third stage including an output terminal, a tenth PMOS transistor, and a tenth NMOS transistors having gate electrodes respectively connected to the pull-up node and the pull-down node of the second stage, the third stage configured to perform a pull-up driving and pull-down driving of the amplified voltage, a first boosting circuit including an eleventh PMOS transistor having a gate electrode connected to the pull-up node and the first boosting circuit configured to increase a current in the first stage, and a second boosting circuit including an eleventh NMOS transistor having a gate electrode connected to the pull-down node and configured to increase the current in the first stage. ## Claims ### Claim 1 An amplifier circuit comprising: a first stage including a first input terminal and a second input terminal, the first stage configured to supply a voltage; a second stage connected to the first stage and configured to amplify the voltage supplied from the first stage, the second stage including a pull-up node and a pull-down node; a third stage including an output terminal, a tenth PMOS transistor having a gate electrode connected to the pull-up node of the second stage, and a tenth NMOS transistor having a gate electrode connected to the pull-down node of the second stage, the third stage configured to perform a pull-up driving of the amplified voltage supplied from the second stage or a pull-down driving of the amplified voltage supplied from the second stage; a first boosting circuit including an eleventh PMOS transistor having a gate electrode connected to the pull-up node included the second stage and the gate electrode of the tenth PMOS transistor included in the third stage, the first boosting circuit configured to increase a current in the first stage while the eleventh PMOS transistor is turned on; and a second boosting circuit including an eleventh NMOS transistor having a gate electrode connected to the pull-down node included the second stage and the gate electrode of the tenth NMOS transistor included in the third stage, the second boosting circuit configured to increase the current in the first stage while the eleventh NMOS transistor is turned on. ### Claim 2 (depends on 1) The amplifier circuit according to claim 1, wherein the first stage further includes: a first PMOS transistor including a gate electrode connected to a direct current (DC) voltage; a first NMOS transistor including a gate electrode connected to the DC voltage; a second PMOS transistor having a gate electrode connected to the first input terminal; a second NMOS transistor having a gate electrode connected to the first input terminal; a third PMOS transistor having a gate electrode connected to the second input terminal; and a third NMOS transistor having a gate electrode connected to the second input terminal, wherein the first input terminal of the first stage is connected to the output terminal of the third stage. ### Claim 3 (depends on 2) The amplifier circuit according to claim 2, wherein a drain electrode of the eleventh PMOS transistor is connected to a source electrode of the second PMOS transistor and a source electrode of the third PMOS transistor, and a drain electrode of the eleventh NMOS transistor is connected to a source electrode of the second NMOS transistor and a source electrode of the third NMOS transistor. ### Claim 4 (depends on 3) The amplifier circuit according to claim 3, wherein the second stage further includes: a fourth PMOS transistor having a gate electrode connected to a PMOS feedback node; a fifth PMOS transistor having a gate electrode connected to the PMOS feedback node; a fourth NMOS transistor having a gate electrode connected to a NMOS feedback node; and a fifth NMOS transistor having a gate electrode connected to the NMOS feedback node. ### Claim 5 (depends on 4) The amplifier circuit according to claim 4, wherein the first boosting circuit further includes a twelfth PMOS transistor having a gate electrode connected to the PMOS feedback node, and the second boosting circuit further includes a twelfth NMOS transistor having a gate electrode connected to the NMOS feedback node. ### Claim 6 (depends on 5) The amplifier circuit according to claim 5, wherein a drain electrode of the twelfth PMOS transistor is connected to the source electrode of the second PMOS transistor and the source electrode of the third PMOS transistor, and a drain electrode of the twelfth NMOS transistor is connected to the source electrode of the second NMOS transistor and the second electrode of the third NMOS transistor. ### Claim 7 (depends on 5) The amplifier circuit according to claim 5, wherein the first boosting circuit further includes a thirteenth PMOS transistor having a gate electrode connected to pull-up node and a fourteenth PMOS transistor having a gate electrode connected to the pull-up node, and the second boosting circuit further includes a thirteenth NMOS transistor having a gate electrode connected to the pull-down node and a fourteenth NMOS transistor having a gate electrode connected to the pull-down node. ### Claim 8 (depends on 7) The amplifier circuit according to claim 7, wherein a drain electrode of the thirteenth PMOS transistor is connected to a drain electrode of the third NMOS transistor, a drain electrode of the fourteenth PMOS transistor is connected to a drain electrode of the second NMOS transistor, a drain electrode of the thirteenth NMOS transistor is connected to a drain electrode of the second PMOS transistor, and a drain electrode of the fourteenth NMOS transistor is connected to a drain electrode of the third PMOS transistor. ### Claim 9 (depends on 1) The amplifier circuit according to claim 1, wherein the amplifier circuit is a unity gain buffer. ### Claim 10 A display apparatus comprising: a display panel including a plurality of pixels, a plurality of gate lines connected to the plurality of pixels, and a plurality of data lines connected to the plurality of pixels; a gate driver configured to drive the plurality of gate lines of the display panel; and a data driver configured to drive the plurality of data lines of the display panel, the data driver including an amplifier circuit that amplifies a data voltage, the amplifier circuit including: a first stage including a first input terminal and a second input terminal, the first input terminal connected to an output terminal of the amplifier circuit that outputs the data voltage; a second stage connected to the first stage and configured to amplify the data voltage, the second stage including a pull-up node and a pull-down node; a third stage including the output terminal of the amplifier circuit that is connected to the first input terminal of the first stage, a pull-up PMOS transistor having a gate electrode connected to the pull-up node of the second stage, a pull-down NMOS transistor having a gate electrode connected to the pull-down node of the second stage, the third stage configured to perform a pull-up driving of the amplified data voltage supplied from the second stage while the pull-up PMOS transistor is turned on or a pull-down driving of the amplified data voltage supplied from the second stage while the pull-down NMOS transistor is turned on; a first boosting circuit including a first boosting PMOS transistor having a gate electrode connected to the pull-up node included in the second stage and the gate electrode of the pull-up PMOS transistor included in the third stage, the first boosting circuit configured to increase a current in the first stage while the first boosting PMOS transistor is turned on; and a second boosting circuit including a first boosting NMOS transistor having a gate electrode connected to the pull-down node included the second stage and the gate electrode of the pull-down NMOS transistor included in the third stage, the second boosting circuit configured to increase the current in the first stage while the first boosting NMOS transistor is turned on. ### Claim 11 (depends on 10) The display apparatus according to claim 10, wherein the amplifier circuit is a unity gain buffer. ### Claim 12 (depends on 10) The display apparatus according to claim 10, wherein the first boosting circuit and the second boosting circuit are included in the first stage. ### Claim 13 (depends on 10) The display apparatus according to claim 10, wherein the first stage further includes: a first PMOS transistor including a gate electrode connected to a direct current (DC) voltage; a first NMOS transistor including a gate electrode connected to the DC voltage; a second PMOS transistor having a gate electrode connected to the first input terminal; a second NMOS transistor having a gate electrode connected to the first input terminal; a third PMOS transistor having a gate electrode connected to the second input terminal; and a third NMOS transistor having a gate electrode connected to the second input terminal. ### Claim 14 (depends on 13) The display apparatus according to claim 13, wherein a drain electrode of the first boosting PMOS transistor is connected to a source electrode of the second PMOS transistor and a source electrode of the third PMOS transistor, and a drain electrode of the first boosting NMOS transistor is connected to a source electrode of the second NMOS transistor and a source electrode of the third NMOS transistor. ### Claim 15 (depends on 14) The display apparatus according to claim 14, wherein the second stage further includes: a fourth PMOS transistor having a gate electrode connected to a PMOS feedback node; a fifth PMOS transistor having a gate electrode connected to the PMOS feedback node; a fourth NMOS transistor having a gate electrode connected to a NMOS feedback node; and a fifth NMOS transistor having a gate electrode connected to the NMOS feedback node. ### Claim 16 (depends on 15) The display apparatus according to claim 15, wherein the first boosting circuit further includes a second boosting PMOS transistor having a gate electrode connected to the PMOS feedback node, the gate electrode of the fourth PMOS transistor, and the gate electrode of the fifth PMOS transistor, and the second boosting circuit further includes a second boosting NMOS transistor having a gate electrode connected to the NMOS feedback node, the gate electrode of the fourth NMOS transistor, and the gate electrode of the fifth NMOS transistor. ### Claim 17 (depends on 16) The display apparatus according to claim 16, wherein the first boosting circuit and the second boosting circuit are included in the first stage. ### Claim 18 (depends on 16) The display apparatus according to claim 16, wherein a drain electrode of the second boosting PMOS transistor is connected to the source electrode of the second PMOS transistor and the source electrode of the third PMOS transistor, and a drain electrode of the second boosting NMOS transistor is connected to the source electrode of the second NMOS transistor and the second electrode of the third NMOS transistor. ### Claim 19 (depends on 16) The display apparatus according to claim 16, wherein the first boosting circuit further includes a third boosting PMOS transistor having a gate electrode connected to pull-up node and a fourth boosting PMOS transistor having a gate electrode connected to the pull-up node, and the second boosting circuit further includes a third boosting NMOS transistor having a gate electrode connected to the pull-down node and a fourth boosting NMOS transistor having a gate electrode connected to the pull-down node. ### Claim 20 (depends on 19) The display apparatus according to claim 19, wherein a drain electrode of the third boosting PMOS transistor is connected to a drain electrode of the third NMOS transistor, a drain electrode of the fourth boosting PMOS transistor is connected to a drain electrode of the second NMOS transistor, a drain electrode of the third boosting NMOS transistor is connected to a drain electrode of the second PMOS transistor, and a drain electrode of the fourth boosting NMOS transistor is connected to a drain electrode of the third PMOS transistor. ### Claim 21 (depends on 19) The display apparatus of claim 19, wherein the first boosting PMOS transistor, the second boosting PMOS transistor, the first boosting NMOS transistor, and the second boosting NMOS transistor are included in the first stage, and the third boosting PMOS transistor, the fourth boosting PMOS transistor, the third boosting NMOS transistor, and the third boosting NMOS transistor are included in the second stage.