Variable gain amplifier circuit and semiconductor integrated circuit

A variable gain amplifier circuit comprising:

• a first input terminal and a second input terminal;
• a first output terminal and a second output terminal;
• a first transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal being electrically connected to the first input terminal, the first current terminal being electrically connected to the first output terminal;
• a second transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal of the second transistor being electrically connected to the second input terminal, the first current terminal of the second transistor being electrically connected to the second output terminal;
• a current source electrically connected between a first power line and the respective second current terminals of the first transistor and the second transistor;
• a first load element electrically connected between the first output terminal and a second power line;
• a second load element electrically connected between the second output terminal and the second power line;
• and
• a variable resistance circuit having a first node and a second node, the first node being connected to the second current terminal of the first transistor, the second node being connected to the second current terminal of the second transistor, the variable resistance circuit being configured to vary a resistance value between the first node and the second node,
• wherein the variable resistance circuit includes
• N (N is an integer of 3 or larger) field effect transistors including a first field effect transistor to an Nth field effect transistor each having two terminals and a control terminal and having the two terminals connected in series between the first node and the second node, the first field effect transistor being connected to the first node, an ith (i is an integer of 2 to N−1) field effect transistor being connected to an i−1th field effect transistor, the Nth field effect transistor being connected between an N−1th field effect transistor and the second node,
• N+1 dividing resistors including a first dividing resistor to an N+1th dividing resistor connected in series between the first node and the second node, the first dividing resistor being connected between the first node and a first dividing node, a jth (j is an integer of 2 to N) dividing resistor being connected between a j−1th dividing node and a jth dividing node, the N+1th dividing resistor being connected between an Nth dividing node and the second node,
• N variable current sources including a first variable current source to an Nth variable current source each providing a variable current,
• N series resistors including a first series resistor to an Nth series resistor, a kth (k is an integer of 1 to N) series resistor being connected between a kth variable current source and the control terminal of a kth field effect transistor, and
• N bias resistors including a first bias resistor to an Nth bias resistor, an mth (m is an integer of 1 to N) bias resistor being connected between an mth dividing node and an mth variable current source.