# US 12,119,776 B2 · Method and circuit arrangement for controlling a stepper motor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,776 B2 - Document ID: US12119776B2 - Status: Granted - Kind: B2 - Application number: 17/154,101 - Filed: 2021-01-21 - Published: 2021-07-22 - Granted: 2024-10-15 - Earliest claimed: 2020-01-21 - Assignees: Maxim Integrated Products, Inc. - Applicants: Maxim Integrated Products, Inc. - Inventors: Bernhard Dwersteg - Web page: https://patentgrep.com/patent/US12119776B2 ## CPC - H02P 8/12: Control or stabilisation of current - H02M 3/3376: {with automatic control of output voltage or current} - H02M 7/5387: in a bridge configuration - H02M 7/5395: by pulse-width modulation - H02P: CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract Described is a method and a circuit arrangement for controlling a stepper motor in a voltage-controlled or voltage-regulated operating mode, having a bridge circuit provided for a motor coil (A) with semiconductor switches (HS1, HS2, LS1, LS2) for applying a first and a second PWM voltage (U(LA1), U(LA2)) having opposite polarity to the motor coil (A) and having a charge pump for switching at least the high-side semiconductor switch (HS1, HS2) of the bridge circuit. Because the charge pump must wait for a blocking or dead time before a further semiconductor switch can be switched after switching a first semiconductor switch, the time interval between a rising edge of one of the two PWM voltages and a subsequent rising edge of the respective other PWM voltage is increased at least until the blocking or dead time of the charge pump has elapsed. ## Claims ### Claim 1 A method for controlling a stepper motor having a bridge circuit provided for a motor coil with semiconductor switches for applying a first and a second PWM voltages having opposite polarity to the motor coil and having a charge pump for switching at least high-side semiconductor switches of the bridge circuit, the charge pump having a blocking or dead time, having the following steps: detecting a time interval between a rising edge of one of the two PWM voltages and a subsequent rising edge of the other respective PWM voltage, delaying the rising edge that occurs later by a delay time that is at least as great as a difference between the blocking or dead time of the charge pump and the detected time interval, in which the blocking or dead time of the charge pump is a predetermined first delay time, and in which the rising edge that occurs later is delayed by a second delay time, which results from the difference between the first delay time and the detected time interval, and delaying a falling edge of the same PWM voltage that follows the rising edge that occurs later by the same delay time. ### Claim 2 (depends on 1) The method according to claim 1, in which the blocking or dead time comprises a period of time required to completely switch through a semiconductor switch and a period of time required to charge capacitors of the charge pump. ### Claim 3 (depends on 1) The method according to claim 1, in which low-side semiconductor switches of the bridge circuit are also switched using the charge pump. ### Claim 4 (depends on 1, 2, 3) A circuit arrangement for controlling a stepper motor in a voltage-controlled or voltage-regulated operating mode, having a bridge circuit provided for a motor coil (A) with semiconductor switches (HS1, HS2, LS1, LS2) for applying a first and a second PWM voltages (U(LA1), U(LA2)) having opposite polarity to the motor coil (A), and having a charge pump for switching at least high-side semiconductor switches (HS1, HS2) of the bridge circuit, the charge pump having a blocking or dead time which is required in order to be able to switch a further semiconductor switch after switching a first semiconductor switch, particularly for carrying out a method according to at least one of claims 1 and 2-3, having the following components: a first and a second L-H edge detectors (11, 21) for detecting a rising edge of the PWM pulses of the first and the second PWM voltages (U(LA1); U(LA2)), respectively, a first and a second H-L edge detector (12, 22) for detecting a falling edge of the PWM pulses of the first and the second PWM voltages (U(LA1); U(LA2)), respectively, a first and a second L-H delay unit (13, 23) for delaying a rising edge of the PWM pulses of the first and the second PWM voltages (U(LA1); U(LA2)), a first and a second H-L delay unit (14, 24) for delaying a falling edge of the PWM pulses of the first and the second PWM voltages (U(LA1); U(LA2)), respectively, a first multiplexer (Mx1) for switching through either the edges of the PWM pulses of the first PWM voltage (U(LA1)) delayed by the first L-H delay unit (13) and by the first H-L delay unit (14) or the undelayed first PWM voltage (U(LA1)) to the bridge circuit, a second multiplexer (Mx2) for switching through either the edges of the PWM pulses of the second PWM voltage (U(LA2)) delayed by the second L-H delay unit (23) and by the second H-L delay unit (24) or the undelayed second PWM voltage (U(LA2)) to the bridge circuit, a first and a second switching units (16, 26) for switching the first and second multiplexers (Mx1, Mx2), respectively, and a time counter (30) acted upon by the first and second L-H edge detectors (11, 21) for detecting a time interval (tx) between a rising edge of the first PWM voltage (U(LA1)) and a subsequent or simultaneous rising edge of the second PWM voltage (U(LA2) and to determine a delay time (t2), which corresponds to a difference between the blocking or dead time of the charge pump and the detected time interval (tx) and with which the following rising edge is to be delayed, for applying said delay time (t2) to the first or second L-H delay unit (13, 23), the first or second H-L delay unit (14, 24) and the first and second switching unit (16, 26). ### Claim 5 (depends on 4) The circuit arrangement according to claim 4, having a priority unit (31) for generating a first and a second selection signals (SelDy A1, SelDy A2) which is supplied to the first and the second switching units (16, 26), respectively, for switching the first and second multiplexers (Mx1, Mx2), respectively, to select the PWM voltages (U(LA1), U(LA2)) of which the rising and falling edges are to be delayed. ### Claim 6 (depends on 4) The circuit arrangement according to claim 4, in which inputs (A1, A2) of which are connected to the outputs of a voltage chopper (CH-U) and the outputs (Ad1, Ad2) of which are connected to the inputs of a driver circuit (Tr) for switching the semiconductor switches of the bridge circuit. ### Claim 7 (depends on 4) The circuit arrangement according to claim 4, in which the bridge circuit constitutes a full bridge having four semiconductor switches or a half bridge having two semiconductor switches. ### Claim 8 (depends on 4) The circuit arrangement according to claim 4, in which the semiconductor switches are MOSFETs.