# US 12,119,771 B2 · Single carrier pulse width modulator for 5-level converter with capacitor voltage self-balancing, equal loss distribution, and improved output voltage spectrum > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,771 B2 - Document ID: US12119771B2 - Status: Granted - Kind: B2 - Application number: 18/000,476 - Filed: 2020-06-12 - Published: 2023-07-13 - Granted: 2024-10-15 - Earliest claimed: 2020-06-12 - Applicants: Socovar, SociéTé En Commandite - Inventors: Mostafa Abarzadeh; Kamal Al-Haddad - Web page: https://patentgrep.com/patent/US12119771B2 ## CPC - H02P 27/14: with three or more levels of voltage - H02M 1/0095: {Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck} - H02M 1/12: Arrangements for reducing harmonics from AC input or output - H02M 7/05: {Capacitor coupled rectifiers} - H02M 7/217: using semiconductor devices only - H02M 7/4837: {Flying capacitor converters} - H02M 7/487: Neutral point clamped inverters - H02M 7/5395: by pulse-width modulation - H02P: CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract The present disclosure provides a method and apparatus using a novel PWM switching technique that requires only one PWM carrier signal and benefits from two logic functions to provide switching signals and provides the flying capacitor (FC) voltage as well as dc-link capacitors voltages regulated to their desired values without external control. It may also, eliminate the odd multiples of the switching harmonic clusters from the output voltage is possible; double the frequency of first switching harmonic; reduce filtering efforts may be required since the values of the output LC filter inductor and capacitor can be very much reduced. Furthermore, notable reduction in control complexity is possible using the novel PWM method. ## Claims ### Claim 1 A multi-level power inverter having a DC input and at least one AC phase output comprising for each one of said at least one AC phase output: two DC capacitors connected in series with said DC input, said DC capacitors, in operation, being charged to one half of a voltage of said DC input; a ground or neutral terminal connected to a midpoint between said two DC capacitors connected in series; a pair of power switches S3 connected in series across a first one of said two DC capacitors; a pair of power switches S4 connected in series across a second one of said two DC capacitors; a flying capacitor, in operation, being charged to one quarter of a voltage of said DC input; a pair of power switches S2, a first one of said power switches S2 connected between a midpoint between said power switches S3 and a first terminal of said flying capacitor and a second one of said power switches S2 connected between a midpoint between said power switches S4 and a second terminal of said flying capacitor; a pair of power switches S1, a first one of said power switches S1 connected between the first terminal of said flying capacitor and one of said at least one AC phase output, and a second one of said power switches S1 connected between the second terminal of said flying capacitor and said one of said at least one AC phase output; and a modulator having an input for receiving a reference waveform signal and gate signal outputs connected to each of said pairs of power switches S1 through S4, wherein said modulator, in operation, produces said gate signal outputs without sensor feedback, cause the flying capacitor to be equally charged and discharged in each pulse-width modulation period for voltage balancing of the flying capacitor, and causes the switching time of said pairs of power switches S3 and S4 to be equal to balance the voltages on said two DC capacitors while canceling odd multiples of a switching harmonic cluster frequency and doubling the switching harmonic cluster frequency. ### Claim 2 (depends on 1) The multi-level power inverter as defined in claim 1, wherein said modulator comprises: at least one zero-crossing detector; two logic function circuits; and a single carrier signal source. ### Claim 3 (depends on 1) The multi-level power inverter as defined in claim 1, wherein said modulator comprises a processor and memory storing instructions that when executed by the processor generate a sequence of said gate signal outputs in accordance with said reference waveform signal. ### Claim 4 (depends on 3) The multi-level power inverter as defined in claim 3, wherein said modulator input comprises waveform characteristic data of said reference waveform signal. ### Claim 5 (depends on 1) The multi-level power inverter as defined in claim 1, wherein said at least one AC phase output comprises three AC phase outputs, said reference waveform signal comprising three reference waveform signals having phases separated by 120 degrees and a common frequency and amplitude. ### Claim 6 (depends on 1) The multi-level power inverter as defined in claim 1, further comprising an LC filter connected to said one of said at least one AC phase output. ### Claim 7 A multi-level power rectifier having a DC output and at least one AC phase input comprising: two DC capacitors connected in series with said DC output, said DC capacitors, in operation, being charged to one half of a voltage of said DC output; for each one of said at least one AC phase input: a ground or neutral terminal connected to a midpoint between said two DC capacitors connected in series; a pair of power switches S3 connected in series across a first one of said two DC capacitors; a pair of power switches S4 connected in series across a second one of said two DC capacitors; a flying capacitor, in operation, being charged to one quarter of a voltage of said DC output; a pair of power switches S2, a first one of said power switches S2 connected between a midpoint between said power switches S3 and a first terminal of said flying capacitor and a second one of said power switches S2 connected between a midpoint between said power switches S4 and a second terminal of said flying capacitor; a pair of power switches S1, a first one of said power switches S1 connected between the first terminal of said flying capacitor and one of said at least one AC phase input, and a second one of said power switches S1 connected between the second terminal of said flying capacitor and said one of said at least one AC phase input; and a current controller receiving phase and current measurements from said at least one AC phase input, a desired DC voltage signal and producing at least one reference waveform signal for each of said at least one AC phase input; a modulator having an input for receiving said at least one reference waveform signal for each of said at least one AC phase input and having gate signal outputs connected to each of said pairs of power switches S1 through S4, wherein said modulator, in operation, produces said gate signal outputs without sensor feedback, cause the flying capacitor to be equally charged and discharged in each pulse-width modulation period for voltage balancing of the flying capacitor, and causes the switching time of said pairs of power switches S3 and S4 to be equal to balance the voltages on said two DC capacitors while canceling odd multiples of a switching harmonic cluster frequency and doubling the switching harmonic cluster frequency. ### Claim 8 (depends on 7) The multi-level power rectifier as defined in claim 7, wherein said modulator comprises: at least one zero-crossing detector; two logic function circuits; and a single carrier signal source. ### Claim 9 (depends on 7) The multi-level power rectifier as defined in claim 7, wherein said modulator comprises a processor and memory storing instructions that when executed by the processor generate a sequence of said gate signal outputs in accordance with said at least one reference waveform signal. ### Claim 10 (depends on 9) The multi-level power rectifier as defined in claim 9, wherein said modulator input comprises waveform characteristic data of at least one said reference waveform signal. ### Claim 11 (depends on 7) The multi-level power rectifier as defined in claim 7, wherein said at least one AC phase input comprises three AC phase inputs, said reference waveform signal comprising three reference waveform signals having phases separated by 120 degrees and a common frequency and amplitude. ### Claim 12 (depends on 7) The multi-level power rectifier as defined in claim 7, further comprising grid filter connected to said one of said at least one AC phase input. ### Claim 13 (depends on 12) The multi-level power rectifier as defined in claim 12, wherein said grid filter comprises an inductance and a resistance for each one of said at least one AC phase input. ### Claim 14 A motor controller comprising: a rectifier for converting AC power to DC power; a multi-level power inverter connected to said rectifier, said multi-level power inverter having a DC input and at least one AC phase output comprising for each one of said at least one AC phase output: two DC capacitors connected in series with said DC input, said DC capacitors, in operation, being charged to one half of a voltage of said DC input; a ground or neutral terminal connected to a midpoint between said two DC capacitors connected in series; a pair of power switches S3 connected in series across a first one of said two DC capacitors; a pair of power switches S4 connected in series across a second one of said two DC capacitors; a flying capacitor, in operation, being charged to one quarter of a voltage of said DC input; a pair of power switches S2, a first one of said power switches S2 connected between a midpoint between said power switches S3 and a first terminal of said flying capacitor and a second one of said power switches S2 connected between a midpoint between said power switches S4 and a second terminal of said flying capacitor; a pair of power switches S1, a first one of said power switches S1 connected between the first terminal of said flying capacitor and one of said at least one AC phase output, and a second one of said power switches S1 connected between the second terminal of said flying capacitor and said one of said at least one AC phase output; and a modulator having an input for receiving a reference waveform signal and gate signal outputs connected to each of said pairs of power switches S1 through S4, wherein said modulator, in operation, produces said gate signal outputs without sensor feedback, cause the flying capacitor to be equally charged and discharged in each pulse-width modulation period for voltage balancing of the flying capacitor, and causes the switching time of said pairs of power switches S3 and S4 to be equal to balance the voltages on said two DC capacitors while canceling odd multiples of a switching harmonic cluster frequency and doubling the switching harmonic cluster frequency; and a controller connected to a motor sensor and to said input of said modulator input for providing said a reference waveform signal. ### Claim 15 (depends on 14) The motor controller as defined in claim 14, wherein said rectifier comprises a multi-level rectifier for converting AC power to DC power having a DC output and at least one AC phase input comprising: two DC capacitors connected in series with said DC output, said DC capacitors, in operation, being charged to one half of a voltage of said DC output; for each one of said at least one AC phase input: a ground or neutral terminal connected to a midpoint between said two DC capacitors connected in series; a pair of power switches S3 connected in series across a first one of said two DC capacitors; a pair of power switches S4 connected in series across a second one of said two DC capacitors; a flying capacitor, in operation, being charged to one quarter of a voltage of said DC output; a pair of power switches S2, a first one of said power switches S2 connected between a midpoint between said power switches S3 and a first terminal of said flying capacitor and a second one of said power switches S2 connected between a midpoint between said power switches S4 and a second terminal of said flying capacitor; a pair of power switches S1, a first one of said power switches S1 connected between the first terminal of said flying capacitor and one of said at least one AC phase input, and a second one of said power switches S1 connected between the second terminal of said flying capacitor and said one of said at least one AC phase input; and a current controller receiving phase and current measurements from said at least one AC phase input, a desired DC voltage signal and producing at least one reference waveform signal for each of said at least one AC phase input: a modulator having an input for receiving said at least one reference waveform signal for each of said at least one AC phase input and having gate signal outputs connected to each of said pairs of power switches S1 through S4, wherein said modulator, in operation, produces said gate signal outputs without sensor feedback, cause the flying capacitor to be equally charged and discharged in each pulse-width modulation period for voltage balancing of the flying capacitor, and causes the switching time of said pairs of power switches S3 and S4 to be equal to balance the voltages on said two DC capacitors while canceling odd multiples of a switching harmonic cluster frequency and doubling the switching harmonic cluster frequency.