# US 12,119,755 B2 · Synchronous rectifier scheme for continuous conduction mode in primary side controlled fly-back converter

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,119,755 B2
- Document ID: US12119755B2
- Status: Granted
- Kind: B2
- Application number: 17/829,130
- Filed: 2022-05-31
- Published: 2023-11-30
- Granted: 2024-10-15
- Earliest claimed: 2022-05-31
- Assignees: Cypress Semiconductor Corporation
- Applicants: Cypress Semiconductor Corporation
- Inventors: Arun Khamesra; Pragyan S. Biswal; Hariom Rai; Saravanan Murugesan
- Web page: https://patentgrep.com/patent/US12119755B2

## CPC

- H02M 3/33592: {having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer}
- H02M 1/0058: {by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero (using an auxiliary actively switched resonant commutation circuit connected to an intermediate DC voltage or between two push-pull branches of an inverter bridge H02M7/4811; in resonant inverters H02M7/4815; in inverters operating from a resonant DC source H02M7/4826)}
- H02M 3/33523: {with galvanic isolation between input and output of both the power stage and the feedback loop}
- H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS

## Abstract

A primary-side-controlled fly-back converter is provided to eliminate cross-conduction between a power-switch (PS) on a primary side and a synchronous-rectifier (SR) on a secondary side when operating in continuous conduction mode (CCM). Generally, the converter includes a transformer having a primary coupled to a rectified AC input through the PS, and a secondary coupled to a DC output through the SR, the SR having a drain coupled to the secondary winding. A fly-back-controller includes a primary-controller operable to control a duty cycle of the PS, and a secondary-controller operable to turn OFF the SR when the PS turns ON in CCM. The secondary-controller includes a CCM zero-crossing-detector comparator having a first input coupled to the drain of the SR through a capacitor, and is operable to detect a sharp change in a drain voltage when the PS turns ON during CCM, and to output a signal to turn OFF the SR.

## Claims

### Claim 1

A Primary Side Controlled (PSC) fly-back converter comprising:
a transformer having a primary winding coupled to a rectified AC input through a power switch (PS), and a secondary winding coupled to a DC output through a synchronous rectifier field effect transistor (SR_FET), the SR_FET having a drain coupled to the secondary winding and a source coupled to the DC output; and
a fly-back-controller implemented as an integrated circuit (IC) comprising:
a primary-side-controller operable to control a duty cycle of the PS based on power supplied to the DC output; and
a secondary-side-controller operable to turn OFF the SR_FET when the PS turns ON in continuous conduction mode (CCM), the secondary-side-controller including a CCM zero-crossing-detector (ZCD) comparator having a first input coupled to the drain of the SR_FET through a capacitor to receive a first voltage, and a second input coupled to receive a second voltage, the CCM ZCD comparator operable to detect a change in a voltage on the drain of the SR_FET during CCM when the PS turning ON causes a change in secondary current, and to output a signal to turn OFF the SR_FET.

### Claim 2 (depends on 1)

The PSC fly-back converter of claim 1 wherein the capacitor through which the first input of the CCM ZCD comparator is coupled to the drain of the SR_FET is an external capacitor (Cext) external to the fly-back-controller, and coupled thereto through a SR_CAP pin on the IC.

### Claim 3 (depends on 2)

The PSC fly-back converter of claim 2, wherein the secondary-side-controller further comprises a clamping circuit coupled between the SR_CAP pin and the first input of the CCM ZCD comparator, the clamping circuit operable so that a voltage on the first input does not exceed +/−0.7 volts.

### Claim 4 (depends on 3)

The PSC fly-back converter of claim 3, wherein the external capacitor has a capacitance of about 10 pico-Farads.

### Claim 5 (depends on 1)

The PSC fly-back converter of claim 1 further comprising a gate drive circuit including a N-type field effect transistor (NFET) through which a gate of the SR_FET can be coupled to ground to turn OFF the SR_FET in response to the signal output by the CCM ZCD comparator.

### Claim 6 (depends on 5)

The PSC fly-back converter of claim 5, wherein the secondary-side-controller further comprises a buffer through which the signal output by the CCM ZCD comparator is coupled to the NFET in the gate drive circuit.

### Claim 7 (depends on 5)

The PSC fly-back converter of claim 5, wherein the gate drive circuit further comprises a first P-type field effect transistor (PFET) and a second PFET coupled in parallel to the gate of the SR_FET, the first PFET operable to turn ON the SR_FET, and the second PFET operable to maintain the SR_FET ON, so that the NFET can quickly turn OFF the SR_FET in response to the signal output by the CCM ZCD comparator.

### Claim 8 (depends on 1)

The PSC fly-back converter of claim 1, wherein the first input is a non-inverting input, the second input is an inverting input and the second voltage is a reference voltage.

### Claim 9 (depends on 8)

The PSC fly-back converter of claim 8, further comprising a resistor coupled between the first input and ground.

### Claim 10 (depends on 1)

The PSC fly-back converter of claim 1, wherein the first input is a non-inverting input, the second input is an inverting input, and wherein the second input is coupled to the drain of the SR_FET through a voltage divider including both an external resistor (Rext) and an internal resistor (Rint) internal to the IC of the fly-back-controller.

### Claim 11 (depends on 10)

The PSC fly-back converter of claim 10, further comprising a resistor coupled between the first input and the second input of the CCM ZCD comparator, wherein a resistance of the resistor defines a common mode input voltage of the CCM ZCD comparator.

### Claim 12 (depends on 10)

The PSC fly-back converter of claim 10 further comprising a discontinuous conduction mode zero-crossing-detector (DCM ZCD) comparator having a first non-inverting input coupled to the drain of the SR_FET through the external resistor of the voltage divider, and a second inverting input coupled to a negative reference voltage, the DCM ZCD comparator operable to detect a zero crossing of the voltage on the drain of the SR_FET when the PSC fly-back converter is operating in discontinuous conduction mode (DCM).

### Claim 13

A Primary Side Controlled (PSC) fly-back converter comprising:
a transformer having a primary winding coupled to a rectified AC input through a power switch (PS), and a secondary winding coupled to a DC output through a synchronous rectifier field effect transistor (SR_FET), the SR_FET having a drain coupled to the secondary winding and a source coupled to the DC output; and
a fly-back-controller implemented as an integrated circuit (IC) comprising:
a primary-side-controller operable to control a duty cycle of the PS based on power supplied to the DC output; and
a secondary-side-controller operable to turn OFF the SR_FET when the PS turns ON in continuous conduction mode (CCM), the secondary-side-controller including a CCM zero-crossing-detector (ZCD) comparator having a first input coupled to the drain of the SR_FET through a capacitor to receive a first voltage, and a second input coupled to the drain of the SR_FET through a voltage divider including both an external resistor (Rext) external to the IC of the fly-back-controller and an internal resistor (Rint), the CCM ZCD comparator operable to detect a change in a voltage on the drain of the SR_FET during CCM when the PS turning ON causes a change in secondary current, and to output a signal to a gate drive circuit to turn OFF the SR_FET.

### Claim 14 (depends on 13)

The PSC fly-back converter of claim 13 wherein the capacitor through which the first input of the CCM ZCD comparator is coupled to the drain of the SR_FET is an external capacitor (Cext) external to the fly-back-controller, and coupled thereto through a SR_CAP pin on the IC, and wherein the secondary-side-controller further comprises a clamping circuit coupled between the SR_CAP pin and the first input of the CCM ZCD comparator, the clamping circuit operable so that a voltage on the first input does not exceed +/−0.7 volts.

### Claim 15 (depends on 13)

The PSC fly-back converter of claim 13, wherein the gate drive circuit further comprises a N-type field effect transistor (NFET) through which the gate of the SR_FET can be coupled to ground to turn OFF the SR_FET in response to the signal output by the CCM ZCD comparator.

### Claim 16 (depends on 15)

The PSC fly-back converter of claim 15, wherein the gate drive circuit further comprises a first P-type field effect transistor (PFET) and a second PFET coupled in parallel to the gate of the SR_FET, the first PFET to turn ON the SR_FET, and the second PFET operable to maintain the SR_FET ON, so that the NFET can quickly turn OFF the SR_FET in response to the signal output by the CCM ZCD comparator.

### Claim 17

A method of operating a Primary Side Controlled (PSC) fly-back converter, the method comprising:
turning ON a power-switch (PS) in a primary side of a transformer while maintaining a synchronous-rectifier (SR) field effect transistor (SR_FET) in a secondary side of the transformer OFF causing a SR drain voltage to rise to a maximum voltage;
turning OFF the PS;
turning ON the SR_FET causing the SR drain voltage to rise at a first rate followed by a continued rise at a second rate, lower than the first rate, as power is drawn from a DC coupled to the secondary side of the transformer through the SR_FET;
turning ON the PS before current in the transformer is completely discharged causing the PSC fly-back converter to operate in a CCM;
sensing through a SR capacitor coupled to the SR drain a resultant rise in the SR drain voltage and coupling the sensed SR drain voltage to a first input of a CCM zero crossing detector (ZCD) comparator;
comparing the sensed SR drain voltage to a voltage coupled to a second input of the CCM ZCD comparator; and
when the SR drain voltage coupled to the first input exceeds the voltage coupled to the second input by a predetermined amount for a predetermined time, outputting a CCM ZCD signal, which causes the SR_FET to turn OFF, eliminating cross-conduction between the PS and the SR_FET when the PSC fly-back converter is operating in CCM.

### Claim 18 (depends on 17)

The method of claim 17 wherein turning ON the SR_FET comprises turning ON the SR_FET by applying a gate voltage to a gate of the SR_FET through a first P-type field effect transistor (PFET) to turn ON the SR_FET, followed by applying the gate voltage to the gate through a second PFET coupled in parallel with the first PFET to the gate of the SR_FET to maintain the SR_FET ON.

### Claim 19 (depends on 17)

The method of claim 17 wherein comparing the sensed SR drain voltage to a voltage coupled to a second input of the CCM ZCD comparator comprises comparing the sensed SR drain voltage to a reference voltage coupled to the second input of the CCM ZCD comparator.

### Claim 20 (depends on 17)

The method of claim 17 wherein comparing the sensed SR drain voltage to a voltage coupled to a second input of the CCM ZCD comparator comprises comparing the sensed SR drain voltage to a voltage coupled to the second input of the CCM ZCD comparator through a voltage divider including an external resistor coupled to the drain of the SR_FET and an internal resistor couple between the external resistor and ground.