# US 12,119,746 B2 · Circuit with voltage controlled oscillator (VCO) circuit and pulse-width modulated (PWM) signal generator, and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,746 B2 - Document ID: US12119746B2 - Status: Granted - Kind: B2 - Application number: 17/807,466 - Filed: 2022-06-17 - Published: 2022-12-29 - Granted: 2024-10-15 - Earliest claimed: 2021-06-29 - Assignees: STMicroelectronics S.r.l. - Applicants: STMicroelectronics S.r.l. - Inventors: Marco Borghese; Mattia Carrera - Web page: https://patentgrep.com/patent/US12119746B2 ## CPC - H02M 3/158: including plural semiconductor devices as final control devices for a single load - H02M 1/0016: {Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters} - H02M 1/0022: {the disturbance parameters being input voltage fluctuations} - H02M 1/0025: {Arrangements for modifying reference values, feedback values or error values in the control loop of a converter} - H02M 3/156: with automatic control of output voltage or current, e.g. switching regulators - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract In an embodiment a circuit includes a voltage-controlled oscillator (VCO) circuit having a first node configured to receive a reference voltage, a second node configured to receive a feedback signal, which is a comparison signal, indicative of a variation of a regulated output voltage of an electronic voltage regulator with respect to the reference voltage and a third node configured to provide a clock signal having a clock period based on the reference voltage and the feedback signal, and a pulse-width modulated (PWM) signal generator circuit having a first node coupled to the VCO circuit and configured to receive the clock signal, a second node configured to receive an input signal proportional to an input voltage signal at an input node of the electronic voltage regulator and a third node configured to provide at least one PWM drive signal to one or more electronic switches of a switching stage based on the clock signal. ## Claims ### Claim 1 A circuit comprising: a voltage-controlled oscillator (VCO) circuit comprising: a first node configured to receive a reference voltage; a second node configured to receive a feedback signal, which is a comparison signal, indicative of a variation of a regulated output voltage of an electronic voltage regulator with respect to the reference voltage; and a third node configured to provide a clock signal having a clock period based on the reference voltage and the comparison signal; and a pulse-width modulated (PWM) signal generator circuit comprising: a first node coupled to the VCO circuit and configured to receive the clock signal; a second node configured to receive an input signal proportional to an input voltage signal at an input node of the electronic voltage regulator; and a third node configured to provide at least one pulse-width modulation (PWM) drive signal to one or more electronic switches of a switching stage of the electronic voltage regulator based on the clock signal, wherein the input signal is proportional to the input voltage signal, and wherein the at least one PWM drive signal has a duty cycle that is inversely proportional to the comparison signal indicative of the variation of the regulated output voltage with respect to the reference voltage. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the switching stage is coupled to a reactive network via a switching node, and wherein the reactive network is connected to ground. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the comparison signal has a DC operating point equivalent to a level of the reference voltage, and wherein an average value of a voltage at the switching node varies as a function of the comparison signal. ### Claim 4 (depends on 3) The circuit of claim 3, wherein the function is a function of a variation in a voltage domain of the comparison signal with respect to the level of the reference voltage. ### Claim 5 (depends on 1) The circuit of claim 1, wherein the VCO circuit comprises: signal processing circuitry coupled to the first node of the VCO circuit and to the second node of the VCO circuit and configured to provide a first signal as a function of the comparison signal and the reference voltage; and a comparator circuit comprising: a first input node coupled to the signal processing circuitry and configured to receive the first signal; a second input node configured to receive a second signal proportional to a level of the reference voltage; and an output node configured to provide the clock signal, wherein the comparator circuit is configured to compare the first signal with the second signal, and produce the clock signal based on a comparison of the first signal with the second signal. ### Claim 6 (depends on 5) The circuit of claim 5, wherein the signal processing circuitry comprises: a current generator configured to produce a reference current based on the level of the reference voltage; and a capacitance comprising: a first capacitance node coupled to the current generator and configured to receive the reference current and coupled to the first input node of the comparator circuit; and a second capacitance node coupled to the second node of the VCO circuit and configured to receive the comparison signal; and a transistor comprising: a control node coupled to the output node of the comparator circuit and configured to receive the clock signal therefrom; a first node coupled to the first capacitance node; and a second node coupled to the second capacitance node, the transistor having a current path therethrough between the first node and the second node, wherein the current path is selectively conductive and non-conductive in response to the clock signal having a first value and a second value, respectively, and wherein the capacitance is charged or discharged as a function of the reference current when the current path through the transistor is non-conductive or conductive in response to the clock signal having the first value and the second value, respectively. ### Claim 7 (depends on 5) The circuit of claim 5, wherein an amplitude of the first signal is inversely proportional to the comparison signal, and wherein the clock period of the clock signal varies as a function of the amplitude of the first signal. ### Claim 8 (depends on 1) The circuit of claim 1, wherein the PWM signal generator circuit is configured to control the duty cycle of the PWM drive signal based on a level of the reference voltage, the input voltage signal and the clock signal. ### Claim 9 (depends on 1) The electronic voltage regulator comprising: a first node configured to receive an input voltage from an energy source; a second node configured to provide the regulated output voltage to a load; a switching node coupled to a reactive network that is connected to ground; a first electronic switch having a current flow path therethrough coupled between the first node and the switching node and a second electronic switch having a current flow path therethrough coupled between a third node and the switching node, the first electronic switch and the second electronic switch having respective control nodes; and the circuit of claim 1, comprising the VCO circuit and the PWM signal generator, coupled to the control nodes of the first and second electronic switches to provide the at least one PWM drive signal based on the clock signal, a level of the input voltage and the reference voltage. ### Claim 10 A method for providing at least one pulse-width modulated (PWM) drive signal, the method comprising: receiving, at a first node of a circuit, a reference voltage; receiving, at a second node of the circuit, a feedback signal, which is a comparison signal, indicative of a variation of a regulated output voltage of an electronic voltage regulator with respect to the reference voltage; and providing, at a third node of the circuit, the at least one PWM drive signal to one or more electronic switches of a switching stage of the electronic voltage regulator, wherein the at least one PWM drive signal, provided by a PWM signal generator circuit, is based on a clock signal and an input signal proportional to an input voltage signal at an input node of the electronic voltage regulator, and wherein the clock signal, provided by a voltage-controlled oscillator (VCO) circuit, has a clock period based on the reference voltage and the comparison signal, wherein the input signal is proportional to the input voltage signal, and wherein the at least one PWM drive signal has a duty cycle that is inversely proportional to the comparison signal indicative of the variation of the regulated output voltage with respect to the reference voltage. ### Claim 11 (depends on 10) The method of claim 10, wherein the switching stage is coupled to a reactive network via a switching node, and wherein the reactive network is connected to ground. ### Claim 12 (depends on 11) The method of claim 11, wherein the comparison signal has a DC operating point equivalent to a level of the reference voltage, and wherein an average value of a voltage at the switching node varies as a function of the comparison signal. ### Claim 13 (depends on 12) The method of claim 12, wherein the function is a function of a variation in a voltage domain of the comparison signal with respect to the level of the reference voltage. ### Claim 14 (depends on 10) The method of claim 10, wherein the at least one PWM drive signal includes the duty cycle based on a level of the reference voltage, the input voltage signal and the clock signal. ### Claim 15 (depends on 10) The method of claim 10, further comprising providing, by a signal processing circuitry of the VCO circuit, a first signal as a function of the comparison signal and the reference voltage to a comparator circuit of the VCO circuit. ### Claim 16 (depends on 15) The method of claim 15, further comprising: receiving, by the comparator circuit, the first signal; receiving, by the comparator circuit, a second signal proportional to a level of the reference voltage; comparing, by the comparator circuit, the first signal with the second signal; and providing the clock signal based on a comparison of the first signal with the second signal. ### Claim 17 (depends on 15) The method of claim 15, wherein an amplitude of the first signal is inversely proportional to the comparison signal, and wherein the clock period of the clock signal varies as a function of the amplitude of the first signal. ### Claim 18 (depends on 15) The method of claim 15, wherein the VCO circuit comprises a current generator for producing a reference current based on a level of the reference voltage. ### Claim 19 (depends on 18) The method of claim 18, further comprising: receiving, by a capacitance of the VCO circuit, the reference current from the current generator; and receiving, by the capacitance, the comparison signal, wherein a transistor is coupled to the capacitance so that a control node of the transistor receives the clock signal and so that a current path of the transistor, coupled between two nodes of the capacitance, is selectively conductive and non-conductive in response to the clock signal having a first value and a second value, respectively, and wherein the capacitance is charged or discharged as a function of the reference current when the current path through the transistor is non-conductive or conductive in response to the clock signal having the first value and the second value, respectively.