# US 12,119,641 B2 · ESD protection for integrated circuit devices

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,119,641 B2
- Document ID: US12119641B2
- Status: Granted
- Kind: B2
- Application number: 18/243,269
- Filed: 2023-09-07
- Published: 2023-12-28
- Granted: 2024-10-15
- Earliest claimed: 2020-03-18
- Applicants: Mavagail Technology, LLC
- Inventors: Darryl G. Walker
- Web page: https://patentgrep.com/patent/US12119641B2

## CPC

- H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits}
- H10D 89/611: {using diodes as protective elements}
- H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices}
- H10D 89/811: {using FETs as protective elements}
- H10D 89/911: {using passive elements as protective elements}
- H10D 89/921: {characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses}
- H10D 89/931: {characterised by the dispositions of the protective arrangements}
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.

## Claims

### Claim 1

A method, comprising:
providing an output buffer circuit in an integrated circuit device, the output buffer circuit having an input terminal and an output terminal, the output buffer circuit including at least one insulated gate field effect transistor (IGFET);
in response to receiving an input signal at the input terminal, providing an output signal at the output terminal that is external to the integrated circuit device; and
providing a first electrostatic discharge (ESD) protection circuit structure coupled to the output terminal, the first ESD protection circuit structure including a first circuit element operating as a diode, the first circuit element including at least three current carrying regions coupled between a first circuit element cathode terminal and a first circuit element anode terminal and disposed in a first direction and are substantially aligned in a second direction substantially perpendicular to the first direction.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
the output buffer circuit includes
a p-type IGFET including a plurality of channels disposed substantially in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction and having a control gate that substantially surrounds the plurality of channels; and
an n-type IGFET including a plurality of channels disposed substantially in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction and having a control gate that substantially surrounds the plurality of channels, the p-type IGFET and n-type IGFET, each have a drain terminal commonly coupled to the first ESD protection circuit structure.

### Claim 3 (depends on 2)

The method of claim 2, wherein:
the p-type IGFET and n-type IGFET, each have a control gate terminal commonly coupled to receive the input signal.

### Claim 4 (depends on 3)

The method of claim 3, further including:
receiving a first power supply potential from a source external to the integrated circuit device; and
the n-type IGFET has a source terminal coupled to receive the first power supply potential.

### Claim 5 (depends on 4)

The method of claim 4, wherein:
the first circuit element cathode terminal coupled to the output terminal and the first circuit element anode terminal coupled to the first power supply potential.

### Claim 6 (depends on 5)

The method of claim 5, further including:
receiving a second power supply potential from a source external to the integrated circuit device; and
the p-type IGFET has a source terminal coupled to receive the second power supply potential.

### Claim 7 (depends on 6)

The method of claim 6, wherein:
the first ESD circuit structure includes a second circuit element operating as a diode, the second circuit element including at least three current carrying regions coupled between a second circuit element cathode terminal and a second circuit element anode terminal and disposed in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction, the second circuit element has the second circuit element cathode terminal coupled to the second power supply potential and the second circuit element anode terminal coupled to the output terminal.

### Claim 8 (depends on 7)

The method of claim 7, wherein:
the first power supply potential is a ground potential.

### Claim 9 (depends on 1)

The method of claim 1, further including:
providing a resistor having a first terminal electrically connected to the output terminal of the output buffer circuit and a second terminal electrically connected to the first ESD protection circuit structure.

### Claim 10 (depends on 1)

The method of claim 1, wherein:
the first circuit element including at least four current carrying regions disposed in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction.

### Claim 11 (depends on 10)

The method of claim 10, wherein:
each current carrying region forms a p-n junction diode.

### Claim 12 (depends on 1)

The method of claim 1, further including:
providing an internal circuit including at least one IGFET including a plurality of channels disposed substantially in the first direction that are substantially aligned in the second direction substantially perpendicular to the first direction, the internal circuit coupled between a first power supply potential and a second power supply potential; and
providing a second ESD protection circuit structure coupled between the first power supply potential and the second power supply potential.

### Claim 13 (depends on 12)

The method of claim 12, wherein:
the second ESD protection circuit structure includes a SCR circuit.

### Claim 14 (depends on 12)

The method of claim 12, wherein:
the internal circuit is not electrically connected to receive an externally provided signal.

### Claim 15

A method, comprising:
providing an output buffer circuit in an integrated circuit device, the output buffer circuit having an input terminal coupled to receive an input signal and an output terminal coupled to provide an output signal, the output buffer circuit including at least one insulated gate field effect transistor (IGFET);
providing a first electrostatic discharge (ESD) protection circuit structure coupled to the output terminal;
providing an internal circuit including at least one IGFET, the internal circuit coupled between a first power supply potential and a second power supply potential; and
providing a second ESD protection circuit structure coupled between the first power supply potential and the second power supply potential;
wherein the output signal is provided external to the integrated circuit device and the first ESD protection circuit structure includes a first circuit element operating as a diode, the first circuit element including at least three current carrying regions disposed in a first direction and are substantially aligned in a second direction substantially perpendicular to the first direction.

### Claim 16 (depends on 15)

The method of claim 15, wherein:
each current carrying region forms a p-n junction diode.

### Claim 17 (depends on 15)

The method of claim 15, wherein:
the first circuit element includes an anode terminal electrically connected to the first power supply potential and a cathode terminal electrically connected to the output terminal and the first power supply potential is a ground potential.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
the internal circuit includes a p-type IGFET including a plurality of channels disposed substantially in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction and an n-type IGFET including a plurality of channels disposed substantially in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction.

### Claim 19 (depends on 18)

The method of claim 18, wherein:
the p-type IGFET and n-type IGFET are configured as an inverter circuit.

### Claim 20 (depends on 15)

The method of claim 15, further including:
providing a substrate with a first region;
forming at least a portion of the second ESD protection circuit structure in the first region;
providing a second region formed over the first region; and
forming the at least one IGFET of the internal circuit in the second region.