# US 12,119,640 B2 · ESD protection circuit

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- Number: US 12,119,640 B2
- Document ID: US12119640B2
- Status: Granted
- Kind: B2
- Application number: 17/831,763
- Filed: 2022-06-03
- Published: 2022-09-15
- Granted: 2024-10-15
- Earliest claimed: 2019-12-06
- Assignees: Huawei Technologies Co., Ltd.
- Applicants: Huawei Technologies Co., Ltd.
- Inventors: Wei Gao; Hongquan Sun; Wangsheng Xie
- Web page: https://patentgrep.com/patent/US12119640B2

## CPC

- H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits}
- H10D 89/611: {using diodes as protective elements}
- H10D 89/811: {using FETs as protective elements}
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An electrostatic discharge (ESD) protection circuit is provided to minimize ESD damage to an internal circuit in a CDM model. The ESD protection circuit includes two stages of discharging circuits that are coupled to an IO pin and the internal circuit, a first power clamp circuit, and a second power clamp circuit. The first power clamp circuit is electrically connected to a power rail and a ground rail to discharge a part of a current to the ground, and the second power clamp circuit is electrically connected to a second-stage discharging circuit and the ground rail, so that the other part of the current is discharged to the ground through the second power clamp circuit.

## Claims

### Claim 1

An electrostatic discharge (ESD) protection circuit, wherein the ESD protection circuit comprises:
a first-stage discharging circuit that is electrically connected to an IO pin, a power rail, and a ground rail;
a first power clamp circuit that is electrically connected to the power rail and the ground rail;
a second-stage discharging circuit that is electrically connected to a protected circuit, and the ground rail; and
a second power clamp circuit that is electrically connected to the second-stage discharging circuit and the ground rail,
wherein
the ESD protection circuit further comprises a bias resistor,
a current input terminal of the second power clamp circuit is electrically connected to the second-stage discharging circuit and a first terminal of the bias resistor,
a pull-down terminal of the second power clamp circuit is electrically connected to the ground rail, and
a second terminal of the bias resistor is electrically connected to the power rail.

### Claim 2 (depends on 1)

The ESD protection circuit according to claim 1, wherein
the second power clamp circuit comprises a first PNP transistor,
a collector of the first PNP transistor is electrically connected to the second-stage discharging circuit and the first terminal of the bias resistor, and
an emitter of the first PNP transistor is electrically connected to the ground rail.

### Claim 3 (depends on 1)

The ESD protection circuit according to claim 1, wherein
the second power clamp circuit comprises a first Zener diode,
a positive electrode of the first Zener diode is electrically connected to the second-stage discharging circuit and the first terminal of the bias resistor, and
a negative electrode of the first Zener diode is electrically connected to the ground rail.

### Claim 4 (depends on 1)

The ESD protection circuit according to claim 1, wherein
the ESD protection circuit further comprises an inter-stage impedance,
the first-stage discharging circuit comprises a first pull-up discharging component and a first pull-down discharging component, wherein
a first terminal of the first pull-up discharging component is electrically connected to the power rail,
a second terminal of the first pull-up discharging component is electrically connected to the IO pin, a first terminal of the first pull-down discharging component, and a first terminal of the inter-stage impedance, and
a second terminal of the first pull-down discharging component is electrically connected to the ground rail, and
the second-stage discharging circuit comprises a second pull-up discharging component and a second pull-down discharging component, wherein
a first terminal of the second pull-up discharging component is electrically connected to the second power clamp circuit,
a second terminal of the second pull-up discharging component is electrically connected to the protected circuit, a first terminal of the second pull-down discharging component, and a second terminal of the inter-stage impedance, and
a second terminal of the second pull-down discharging component is electrically connected to the ground rail.

### Claim 5 (depends on 4)

The ESD protection circuit according to claim 4, wherein the first pull-up discharging component, the first pull-down discharging component, the second pull-up discharging component, and the second pull-down discharging component each comprise a diode or a silicon controlled rectifier.

### Claim 6 (depends on 1)

The ESD protection circuit according to claim 1, wherein the first power clamp circuit comprises a second Zener diode.

### Claim 7 (depends on 1)

The ESD protection circuit according to claim 1, wherein the first power clamp circuit comprises a second PNP transistor.

### Claim 8 (depends on 1)

The ESD protection circuit according to claim 1, wherein the first power clamp circuit comprises a second RC power clamp circuit.

### Claim 9

An apparatus, comprising a chip and an electrostatic discharge (ESD) protection circuit, wherein
the chip comprises an IO pin and a protected circuit, and
the ESD protection circuit comprises:
a first-stage discharging circuit that is electrically connected to the IO pin, a power rail, and a ground rail;
a first power clamp circuit that is electrically connected to the power rail and the ground rail;
a second-stage discharging circuit that is electrically connected to the protected circuit, and the ground rail; and
a second power clamp circuit that is electrically connected to the second-stage discharging circuit and the ground rail,
the ESD protection circuit further comprises a bias resistor,
a current input terminal of the second power clamp circuit is electrically connected to the second-stage discharging circuit and a first terminal of the bias resistor,
a pull-down terminal of the second power clamp circuit is electrically connected to the ground rail, and
a second terminal of the bias resistor is electrically connected to the power rail.

### Claim 10 (depends on 9)

The apparatus according to claim 9, wherein
the second power clamp circuit comprises a first PNP transistor,
a collector of the first PNP transistor is electrically connected to the second-stage discharging circuit and the first terminal of the bias resistor, and
an emitter of the first PNP transistor is electrically connected to the ground rail.

### Claim 11 (depends on 9)

The apparatus according to claim 9, wherein
the second power clamp circuit comprises a first Zener diode,
a positive electrode of the first Zener diode is electrically connected to the second-stage discharging circuit and the first terminal of the bias resistor, and
a negative electrode of the first Zener diode is electrically connected to the ground rail.

### Claim 12 (depends on 9)

The apparatus according to claim 9, wherein
the ESD protection circuit further comprises an inter-stage impedance,
the first-stage discharging circuit comprises a first pull-up discharging component and a first pull-down discharging component, wherein
a first terminal of the first pull-up discharging component is electrically connected to the power rail,
a second terminal of the first pull-up discharging component is electrically connected to the IO pin, a first terminal of the first pull-down discharging component, and a first terminal of the inter-stage impedance, and
a second terminal of the first pull-down discharging component is electrically connected to the ground rail, and
the second-stage discharging circuit comprises a second pull-up discharging component and a second pull-down discharging component, wherein
a first terminal of the second pull-up discharging component is electrically connected to the second power clamp circuit,
a second terminal of the second pull-up discharging component is electrically connected to the protected circuit, a first terminal of the second pull-down discharging component, and a second terminal of the inter-stage impedance, and
a second terminal of the second pull-down discharging component is electrically connected to the ground rail.

### Claim 13 (depends on 12)

The apparatus according to claim 12, wherein the first pull-up discharging component, the first pull-down discharging component, the second pull-up discharging component, and the second pull-down discharging component each comprise a diode or a silicon controlled rectifier.

### Claim 14 (depends on 9)

The apparatus according to claim 9, wherein the first power clamp circuit comprises:
a second Zener diode,
a second PNP transistor, or
a second RC power clamp circuit.