# US 12,119,412 B2 · Semiconductor vertical Schottky diode and method of manufacturing thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,119,412 B2
- Document ID: US12119412B2
- Status: Granted
- Kind: B2
- Application number: 17/276,894
- Filed: 2019-09-20
- Published: 2021-11-11
- Granted: 2024-10-15
- Earliest claimed: 2018-09-21
- Assignees: Lfoundry S.R.L.
- Applicants: Lfoundry S.R.L.
- Inventors: Carsten Schmidt; Gerhard Spitzlsperger
- Web page: https://patentgrep.com/patent/US12119412B2

## CPC

- H10D 8/60: Schottky-barrier diodes
- H10D 8/051: {of Schottky diodes}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 64/23: Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor vertical Schottky diode device, having: a substrate of semiconductor material, with a front surface and a back surface; a lightly doped region formed in a surface portion of the substrate facing the front surface, having a first conductivity type; a first electrode formed on the lightly doped region on the front surface of the substrate, to establish a Schottky contact; a highly doped region at the back surface of the substrate, in contact with the lightly doped region and having the first conductivity type; and a second electrode electrically in contact with the highly doped region, on the back surface of the substrate, to establish an Ohmic contact.

## Claims

### Claim 1

A semiconductor device comprising an integrated vertical Schottky diode, said device comprising:
a substrate of semiconductor material, having a front surface and a back surface and an integrated circuit formed therein;
a lightly doped region formed in a surface portion of the substrate facing the front surface, having a first conductivity type;
a first electrode formed on the lightly doped region on the front surface of the substrate, to establish a Schottky contact;
a highly doped region at the back surface of the substrate, in contact with the lightly doped region and having the first conductivity type;
a second electrode electrically in contact with the highly doped region, on the back surface of the substrate, to establish an Ohmic contact;
further comprising an intermetal dielectric layer on the front surface of the substrate and at least a first frontside interconnection metal layer arranged in the intermetal dielectric layer above said front surface;
a first interconnection pad defined in said first frontside interconnection metal layer and providing a first electrical contact available at the front surface, electrically contacting said first electrode via contacts extending through said intermetal dielectric layer;
a second interconnection pad defined in said first frontside interconnection metal layer to provide a second electrical contact available at said front surface;
a further intermetal dielectric layer above the back surface of the substrate and at least a first backside interconnection metal layer defining at least a first interconnection region arranged in the further intermetal dielectric layer;
further comprising a through silicon via structure, including a dielectric liner and a conductive filling, and laterally enclosing said lightly doped region and said highly doped region, providing an electrical isolation, wherein said through silicon via structure:
extends from said second interconnection pad to said at least first interconnection region which is in electrical contact with the second electrode, the conductive filling of the through silicon via structure establishing an electrical contact between the second electrode and the second interconnection pad,
or extends from the first interconnection pad to a second interconnection region, the conductive filling of the through silicon via structure establishing an electrical contact between the first electrode and the second interconnection region, which thereby provides a first electrical contact available at said back surface.

### Claim 2 (depends on 1)

The device according to claim 1, further comprising a carrier wafer bonded to a top surface of said intermetal dielectric layer.

### Claim 3 (depends on 1)

The device according to claim 1, wherein said first electrode is formed of a metal silicide layer.

### Claim 4 (depends on 1)

The device according to claim 1, further comprising a guard ring, constituted by a doped region of a second conductivity type, opposite to the first conductivity type, arranged in a perimeter region of the lightly doped region at the front surface of the substrate.

### Claim 5 (depends on 4)

The device according to claim 4, wherein the guard ring: overlaps and is in contact with the first electrode; or does not contact the first electrode and is floating.

### Claim 6 (depends on 1)

The device according to claim 1, further comprising a grid of doped regions of a second conductivity type, opposite to the first conductivity type, arranged in the lightly doped region at the front surface of the substrate, having identical width and being equidistant.

### Claim 7 (depends on 1)

The device according to claim 1, further comprising a deep-trench isolation region of a dielectric material, extending from the back surface of the substrate to a shallow-trench isolation formed in the lightly doped region at the frontside surface of the substrate; said shallow-trench isolation and deep-trench isolation region jointly laterally enclosing said lightly doped region and said highly doped region providing a dielectric isolation.

### Claim 8 (depends on 2)

The device according to claim 2, wherein said first electrode is formed of a metal silicide layer.