# US 12,119,409 B2 · Multi-layer crystalline back gated thin film transistor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,119,409 B2
- Document ID: US12119409B2
- Status: Granted
- Kind: B2
- Application number: 18/345,641
- Filed: 2023-06-30
- Published: 2023-11-02
- Granted: 2024-10-15
- Earliest claimed: 2021-09-13
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Van H. Le; Abhishek A. Sharma; Gilbert Dewey; Kent Millard; Jack Kavalieros; Shriram Shivaraman; Tristan A. Tronic; Sanaz Gardner; Justin R. Weber; Tahir Ghani; Li Huey Tan; Kevin Lin
- Web page: https://patentgrep.com/patent/US12119409B2

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10B 12/05: {Making the transistor}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/882: {Compounds of sulfur, selenium or tellurium, e.g. chalcogenides}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- H10N 70/884: {based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883)}
- H10D 62/82: Heterojunctions
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

An integrated circuit includes: a gate dielectric; a first layer adjacent to the gate dielectric; a second layer adjacent to the first layer, the second layer comprising an amorphous material; a third layer adjacent to the second layer, the third layer comprising a crystalline material; and a source or drain at least partially adjacent to the third layer. In some cases, the crystalline material of the third layer is a first crystalline material, and the first layer comprises a second crystalline material, which may be the same as or different from the first crystalline material. In some cases, the gate dielectric includes a high-K dielectric material. In some cases, the gate dielectric, the first layer, the second layer, the third layer, and the source or drain are part of a back-gate transistor structure (e.g., back-gate TFT), which may be part of a memory structure (e.g., located within an interconnect structure).

## Claims

### Claim 1

An integrated circuit comprising:
a gate dielectric;
a first layer adjacent to the gate dielectric;
a second layer adjacent to the first layer, the second layer comprising an amorphous material;
a third layer adjacent to the second layer, the third layer comprising a crystalline material; and
a source or drain at least partially adjacent to the third layer.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the crystalline material of the third layer is a first crystalline material, and wherein the first layer comprises a second crystalline material.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, wherein the first and second crystalline materials are the same material.

### Claim 4 (depends on 2)

The integrated circuit of claim 2, wherein the first and second crystalline materials are elementally different.

### Claim 5 (depends on 2)

The integrated circuit of claim 2, wherein: the first crystalline material includes indium, gallium, zinc, yttrium, tin, silicon, germanium, molybdenum, selenium, tungsten, sulfur, tellurium, or oxygen, or a combination of these; and/or the second crystalline material includes indium, gallium, zinc, yttrium, tin, silicon, germanium, molybdenum, selenium, tungsten, sulfur, tellurium, or oxygen, or a combination of these.

### Claim 6 (depends on 2)

The integrated circuit of claim 2, wherein: the first crystalline material includes one or more transition metal dichalcogenides (TMDs); and/or the second crystalline material includes one or more TMDs.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, wherein the one or more TMDs include one or more of molybdenum disulfide, tungsten disulfide, molybdenum diselenide, tungsten diselenide, or molybdenum ditelluride, or a combination of these.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, wherein the gate dielectric includes a high-K dielectric material.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, wherein the source or drain comprises titanium, nitrogen, tungsten, carbon, platinum, chromium, hafnium, or tantalum, or a combination of these.

### Claim 10 (depends on 1)

The integrated circuit of claim 1, wherein the amorphous material of the second layer includes indium, gallium, zinc, or oxygen, or a combination of these.

### Claim 11 (depends on 1)

The integrated circuit of claim 1, further comprising a gate electrode below the gate dielectric, wherein the source or drain and the gate electrode comprise titanium, nitrogen, tungsten, carbon, platinum, chromium, hafnium, or tantalum, or a combination of these.

### Claim 12 (depends on 1)

The integrated circuit of claim 1, wherein the gate dielectric, the first layer, the second layer, the third layer, and the source or drain are part of a back-gate thin film transistor (TFT) memory device structure.

### Claim 13 (depends on 12)

The integrated circuit of claim 12, comprising:
a device layer including one or more transistors; and
an interconnect layer above the device layer;
wherein the TFT memory device structure is at least partially located within the interconnect layer.

### Claim 14 (depends on 1)

The integrated circuit of claim 1, comprising:
a device layer including one or more transistors; and
an interconnect layer above the device layer;
wherein the gate dielectric, the first layer, the second layer, the third layer, and the source or drain are each at least partially located in the interconnect layer.

### Claim 15

An integrated circuit comprising:
a gate structure including a gate dielectric above a gate electrode;
a stack of layers on the gate dielectric and including (i) a first layer comprising a crystalline material, and (ii) a second layer below the first layer and comprising an amorphous material;
a source at least partially on a first portion of an upper surface of the stack of layer; and
a drain at least partially on a second portion of the upper surface of the stack of layer.

### Claim 16 (depends on 15)

The integrated circuit of claim 15, wherein the crystalline material of the first layer is a first crystalline material, and the stack of layers further includes a third layer comprising a second crystalline material, the third layer between the second layer and the gate dielectric.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, wherein the first crystalline material is the same as the second crystalline material.

### Claim 18

An integrated circuit comprising:
a gate structure including a gate dielectric above a gate electrode, the gate dielectric including a high-K dielectric material;
a stack of layers above and on the high-K dielectric material of the gate dielectric, the stack of layers including first, second, and third layers, the first and third layers comprising crystalline material, and the second layer comprising an amorphous material, wherein the second layer is between the first and third layers and in direct contact with the first and third layers;
a source at least partially on a first portion of an upper surface of the stack of layers;
a drain at least partially on a second portion of the upper surface of the stack of layers;
a first layer of insulator material adjacent a sidewall of the stack of layers; and
a second layer of insulator material laterally between the source and the drain.

### Claim 19 (depends on 18)

The integrated circuit of claim 18, wherein the gate structure, the stack of layers, the source, and the drain are part of a back-gate transistor structure.

### Claim 20 (depends on 19)

The integrated circuit of claim 19, wherein the back-gate transistor structure is positioned in one or more interconnect layers, and coupled to a capacitor, a word-line, and/or a bit-line.