# US 12,119,404 B2 · Gate all around structure with additional silicon layer and method for forming the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,119,404 B2
- Document ID: US12119404B2
- Status: Granted
- Kind: B2
- Application number: 18/344,057
- Filed: 2023-06-29
- Published: 2023-10-26
- Granted: 2024-10-15
- Earliest claimed: 2019-09-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Han Wang; Pei-Hsun Wang; Chun-Hsiung Lin; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US12119404B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/119: {Nanowire, nanosheet or nanotube semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/364: {of IGFETs}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3426: {Oxides}
- H10P 14/3462: {Nanowires}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first semiconductor material layers and second semiconductor layers over a substrate and patterning the first semiconductor material layers and the second semiconductor layers to form a first fin structure and a second fin structure. The method also includes forming an insulating layer around the first fin structure and the second fin structure and forming a dielectric fin structure over the insulating layer and spaced apart from the first fin structure and the second fin structure. The method also includes forming a first source/drain structure attached to the first fin structure and forming a semiconductor layer covering the first source/drain structure. The method also includes oxidizing the semiconductor layer to form an oxide layer and forming a second source/drain structure attached to the second fin structure after the oxide layer is formed.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
alternately stacking first semiconductor material layers and second semiconductor layers in a first direction over a substrate;
patterning the first semiconductor material layers and the second semiconductor layers to form a first fin structure longitudinally oriented along a second direction and a second fin structure longitudinally oriented along a second direction, wherein the first fin structure and the second fin structure are spaced apart from each other in a third direction;
forming an insulating layer around the first fin structure and the second fin structure;
forming a dielectric fin structure over the insulating layer and spaced apart from the first fin structure and the second fin structure in the third direction;
forming a first source/drain structure attached to the first fin structure in the second direction;
forming a semiconductor layer covering the first source/drain structure in the first direction;
oxidizing the semiconductor layer to form an oxide layer; and
forming a second source/drain structure attached to the second fin structure in the second direction after the oxide layer is formed.

### Claim 2 (depends on 1)

The method for manufacturing the semiconductor structure as claimed in claim 1, further comprising:
recessing the insulating layer after forming the dielectric fin structure,
wherein a top surface of the dielectric fin structure, a top surface of the insulating layer, and a top surface of the first fin structure are substantially level with each other before recessing the insulating layer, and the top surface of the insulating layer is lower than the top surface of the dielectric fin structure and the top surface of the first fin structure after recessing the insulating layer.

### Claim 3 (depends on 2)

The method for manufacturing the semiconductor structure as claimed in claim 2, further comprising:
forming a first fin spacer and a second fin spacer over the insulating layer after recessing the insulating layer,
wherein the first fin spacer is sandwiched between the first fin structure and the dielectric fin structure in the third direction, and the second fin spacer is sandwiched between the second fin structure and the dielectric fin structure in the third direction.

### Claim 4 (depends on 1)

The method for manufacturing the semiconductor structure as claimed in claim 1, further comprising:
removing the oxide layer after forming the second source/drain structure.

### Claim 5 (depends on 1)

The method for manufacturing the semiconductor structure as claimed in claim 1, further comprising:
forming a mask layer covering the second fin structure and a portion of the dielectric fin structure.

### Claim 6 (depends on 5)

The method for manufacturing the semiconductor structure as claimed in claim 5, further comprising:
forming a Si layer over the first source/drain structure before forming the semiconductor layer; and
removing the mask layer after forming the semiconductor layer.

### Claim 7 (depends on 1)

The method for manufacturing the semiconductor structure as claimed in claim 1, further comprising:
removing the first semiconductor material layers;
forming a gate structure longitudinally oriented along the third direction and wrapping around the second semiconductor layers; and
forming a gate spacer over a sidewall of the gate structure,
wherein the gate spacer is in direct contact with the oxide layer in the third direction.

### Claim 8

A semiconductor structure, comprising:
a substrate;
channel layers vertically stacked over the substrate in a first direction;
a first dielectric fin structure formed at a first side of the channel layers and longitudinally oriented along a second direction different from the first direction;
a second dielectric fin structure formed at a first side of the channel layers and longitudinally oriented along the second direction;
a gate structure wrapping around the channel layers and longitudinally oriented along a third direction different from the first direction and the second direction;
a source/drain structure attached to the channel layers and sandwiched between the first dielectric fin structure and the second dielectric fin structure; and
a Si layer having a first portion sandwiched between the first dielectric fin structure and the source/drain structure and a second portion sandwiched between the second dielectric fin structure and the source/drain structure.

### Claim 9 (depends on 8)

The semiconductor structure as claimed in claim 8, further comprising:
a fin structure protruding from the substrate; and
an insulating layer formed around the fin structure,
wherein a bottom portion of the first dielectric fin structure is surrounded by the insulating layer.

### Claim 10 (depends on 9)

The semiconductor structure as claimed in claim 9, wherein a top surface of the first dielectric fin structure is higher than a top surface of the insulating layer.

### Claim 11 (depends on 9)

The semiconductor structure as claimed in claim 9, further comprising:
a fin spacer formed over the insulating layer and sandwiched between the first dielectric fin structure and the source/drain structure in the third direction.

### Claim 12 (depends on 11)

The semiconductor structure as claimed in claim 11, wherein a top surface of the first dielectric fin structure is higher than a top surface of the fin spacer.

### Claim 13 (depends on 12)

The semiconductor structure as claimed in claim 12, wherein an air gap is enclosed by the fin spacer, the first dielectric fin structure, and the source/drain structure.

### Claim 14 (depends on 12)

The semiconductor structure as claimed in claim 12, wherein the fin spacer comprises:
a first spacer layer in direct contact with the fin structure and the first dielectric fin structure; and
a second spacer layer formed over the first spacer layer and spaced apart from the source/drain structure and the first dielectric fin structure.

### Claim 15

A semiconductor structure, comprising:
first channel layers stacked along a first direction;
second channel layers stacked along the first direction;
a first source/drain structure attaching to the first channel layers;
a second source/drain structure attaching to the second channel layers;
a dielectric feature formed between the first source/drain structure and the second source/drain structure and extending along a second direction different from the first direction;
a Si layer formed over the first source/drain structure; and
a first contact formed over the first source/drain structure and in direct contact with the Si layer.

### Claim 16 (depends on 15)

The semiconductor structure as claimed in claim 15, further comprising:
a second contact formed over the second source/drain structure; and
a contact etch stop layer formed over the first source/drain structure, the dielectric feature, and the second source/drain structure.

### Claim 17 (depends on 16)

The semiconductor structure as claimed in claim 16, wherein the contact etch stop layer is in direct contact with the second source/drain structure and is separated from the first source/drain structure by the Si layer.

### Claim 18 (depends on 15)

The semiconductor structure as claimed in claim 15, further comprising:
an oxide layer covering a top surface of the Si layer,
wherein the first contact has a sidewall in contact with the Si layer and the oxide layer.

### Claim 19 (depends on 18)

The semiconductor structure as claimed in claim 18, further comprising:
a Ge layer vertically sandwiched between the Si layer and the oxide layer.

### Claim 20 (depends on 18)

The semiconductor structure as claimed in claim 18, wherein the oxide layer comprises Ge.