# US 12,119,403 B2 · Gate structure and method with enhanced gate contact and threshold voltage

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,119,403 B2
- Document ID: US12119403B2
- Status: Granted
- Kind: B2
- Application number: 18/355,997
- Filed: 2023-07-20
- Published: 2024-01-18
- Granted: 2024-10-15
- Earliest claimed: 2017-11-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Max Liu; Yen-Ming Peng; Wei-Shuo Ho
- Web page: https://patentgrep.com/patent/US12119403B2

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3444: {P-type}
- H10P 14/3802: {Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth}
- H10P 52/402: {of semiconductor materials}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.

## Claims

### Claim 1

A method, comprising:
forming isolation features in a substrate, defining first fins in a first region and second fins in a second region;
forming a first dummy gate stack on the first fins and a second dummy gate stack on the second fins;
depositing an inter-layer dielectric (ILD) layer on the substrate;
removing the first and second dummy gate stacks by an etching process, resulting a first gate trench and a second gate trench in the ILD layer;
depositing a first tantalum titanium nitride layer in the first and second gate trenches;
depositing a titanium aluminum nitride layer on the first tantalum titanium nitride layer to fill in the first and second gate trench;
performing an etching process to the titanium aluminum nitride layer in the first gate trench while the second region is protected from the etching process;
depositing a second tantalum titanium nitride layer in the first gate trench; and
filling a low resistance metal in the first gate trench, thereby forming a first gate stack in the first gate trench and a second gate stack in the second gate trench.

### Claim 2 (depends on 1)

The method of claim 1, wherein the filling the low resistance metal in the first gate trench includes depositing one of tungsten, copper, aluminum, copper aluminum alloy and a combination thereof.

### Claim 3 (depends on 2)

The method of claim 2, prior to the performing an etching process to the titanium aluminum nitride layer in the first gate trench, further comprising forming a patterned mask to cover the second region and uncover the first region.

### Claim 4 (depends on 2)

The method of claim 2, wherein the performing of the etching process to the titanium aluminum nitride layer in the first gate trench includes partially removes the titanium aluminum nitride layer in the first gate trench.

### Claim 5 (depends on 1)

The method of claim 1, prior to the depositing of the first tantalum titanium nitride layer, further comprising depositing a high-k dielectric material layer in the first and second gate trenches.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first gate stack includes a first segment on the first fins and a second segment being extended from the first fins onto a shallow trench isolation (STI) feature.

### Claim 7 (depends on 6)

The method of claim 6, wherein the second segment of the first gate stack includes the first and second tantalum titanium nitride layers with the titanium aluminum nitride layer interposed therebetween.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first segment of the first gate stack defines a first air gap surrounded by the second tantalum titanium nitride layer while the second segment is free of void.

### Claim 9 (depends on 8)

The method of claim 8, wherein the second gate stack includes a third segment on the second fins and a fourth segment being extended from the second fins onto the STI feature.

### Claim 10 (depends on 9)

The method of claim 9, wherein the fourth segment of the second gate stack defines a second air gap surrounded by the first tantalum titanium nitride layer and the third segment of the second gate stack defines a third air gap surrounded by the first tantalum titanium nitride layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein the third air gap in the third segment of the second gate stack has a volume being greater than that of the second air gap in the fourth segment of the second gate stack.

### Claim 12

A method, comprising:
forming isolation features in a substrate, defining first fins in a first region and second fins in a second region;
forming a first dummy gate stack on the first fins and a second dummy gate stack on the second fins;
depositing an inter-layer dielectric (ILD) layer on the substrate;
removing the first and second dummy gate stacks by an etching process, resulting in a first gate trench and a second gate trench in the ILD layer;
depositing a high-k dielectric material layer in the first and second gate trenches;
depositing a first tantalum titanium nitride layer over the high-k dielectric material layer in the first and second gate trenches;
depositing a titanium aluminum nitride layer on the first tantalum titanium nitride layer to fill in the first and second gate trench;
performing an etching process to the titanium aluminum nitride layer in the first gate trench such that the titanium aluminum nitride layer in the first gate trench is recessed; and
filling a low resistance metal in the first gate trench, thereby forming a first gate stack in the first gate trench and a second gate stack in the second gate trench, and wherein the first and second gate stacks are different in structure.

### Claim 13 (depends on 12)

The method of claim 12, wherein the filling the low resistance metal in the first gate trench includes depositing one of tungsten, copper, aluminum, copper aluminum alloy and a combination thereof.

### Claim 14 (depends on 12)

The method of claim 12, prior to the filling a low resistance metal in the first gate trench, further comprising depositing a second tantalum titanium nitride layer on the recessed titanium aluminum nitride layer in the first gate trench.

### Claim 15 (depends on 14)

The method of claim 14, prior to the performing an etching process to the titanium aluminum nitride layer in the first gate trench, further comprising forming a patterned mask to cover the second region and uncover the first region.

### Claim 16 (depends on 14)

The method of claim 14, wherein
the first gate stack includes a first segment on the first fins and a second segment being extended from the first fins onto a shallow trench isolation (STI) feature;
the second segment of the first gate stack includes the first and second tantalum titanium nitride layers with the titanium aluminum nitride layer interposed therebetween; and
the first segment of the first gate stack defines a first air gap surrounded by the second tantalum titanium nitride layer while the second segment is free of void.

### Claim 17 (depends on 16)

The method of claim 16, wherein
the second gate stack includes a third segment on the second fins and a fourth segment being extended from the second fins onto the STI feature;
the fourth segment of the second gate stack defines a second air gap surrounded by the first tantalum titanium nitride layer;
the third segment of the second gate stack defines a third air gap surrounded by the first tantalum titanium nitride layer; and
the third air gap in the third segment of the second gate stack has a volume being greater than that of the second air gap in the fourth segment of the second gate stack.

### Claim 18

A method, comprising:
forming isolation features in a substrate, defining first fins in a first region and second fins in a second region;
forming a first dummy gate stack on the first fins and a second dummy gate stack on the second fins;
depositing an inter-layer dielectric (ILD) layer on the substrate;
removing the first and second dummy gate stacks by an etching process, resulting a first gate trench and a second gate trench in the ILD layer;
depositing a high-k dielectric material layer in the first and second gate trenches;
depositing a first tantalum titanium nitride layer in the first and second gate trenches;
depositing a titanium aluminum nitride layer on the first tantalum titanium nitride layer to fill in the first and second gate trench;
performing an etching process to the titanium aluminum nitride layer in the first gate trench such that the titanium aluminum nitride layer is recessed while the second region is protected from the etching process;
depositing a second tantalum titanium nitride layer on the recessed titanium aluminum nitride layer in the first gate trench; and
filling a low resistance metal in the first gate trench, thereby forming a first gate stack is formed in the first gate trench and a second gate stack in the second gate trench, and wherein the first gate stack is free of the low resistance metal.

### Claim 19 (depends on 18)

The method of claim 18, wherein the filling the low resistance metal in the first gate trench includes depositing one of tungsten, copper, aluminum, copper aluminum alloy and a combination thereof.

### Claim 20 (depends on 18)

The method of claim 18, wherein
the first gate stack includes a first segment on the first fins and a second segment being extended from the first fins onto a shallow trench isolation (STI) feature;
the second segment of the first gate stack includes the first and second tantalum titanium nitride layers with the titanium aluminum nitride layer interposed therebetween;
the first segment of the first gate stack defines a first air gap surrounded by the second tantalum titanium nitride layer while the second segment is free of void;
the second gate stack includes a third segment on the second fins and a fourth segment being extended from the second fins onto the STI feature;
the fourth segment of the second gate stack defines a second air gap surrounded by the first tantalum titanium nitride layer;
the third segment of the second gate stack defines a third air gap surrounded by the first tantalum titanium nitride layer; and
the third air gap in the third segment of the second gate stack has a volume being greater than that of the second air gap in the fourth segment of the second gate stack.