# US 12,119,402 B2 · Semiconductor devices with ferroelectric layer and methods of manufacturing thereof

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- Number: US 12,119,402 B2
- Document ID: US12119402B2
- Status: Granted
- Kind: B2
- Application number: 18/308,791
- Filed: 2023-04-28
- Published: 2023-08-24
- Granted: 2024-10-15
- Earliest claimed: 2021-08-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yen-Chieh Huang; Po-Ting Lin; Hai-Ching Chen; Sai-Hooi Yeong; Yu-Ming Lin; Chung-Te Lin
- Web page: https://patentgrep.com/patent/US12119402B2

## CPC

- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/674: {characterised by the active materials}
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10D 64/689: {having ferroelectric layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.

## Claims

### Claim 1

A ferroelectric semiconductor device, comprising:
a substrate;
a blocking layer disposed on a channel of the substrate;
a first seed layer disposed on the blocking layer;
a ferroelectric gate layer formed on the first seed layer; and
an electrode formed over the ferroelectric gate layer;
wherein the first seed layer is arranged to increase an orthorhombic phase fraction of the ferroelectric gate layer and the blocking layer is arranged to increase a band offset between the channel and the blocking layer and to reduce oxygen vacancies between the blocking layer and the channel.

### Claim 2 (depends on 1)

The ferroelectric semiconductor device of claim 1, further comprising a second seed layer disposed on the ferroelectric gate layer, the second seed layer arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.

### Claim 3 (depends on 2)

The ferroelectric semiconductor device of claim 2, wherein the electrode is disposed on the second seed layer.

### Claim 4 (depends on 1)

The ferroelectric semiconductor device of claim 1, wherein the first seed layer is arranged to increase a ratio of (O+T+C)/(O+T+C+M), wherein O is the orthorhombic fraction of the ferroelectric gate layer, T is the tetragonal fraction of the ferroelectric gate layer, C is the cubic fraction of the ferroelectric gate layer, and M is the monoclinic fraction of the ferroelectric gate layer.

### Claim 5 (depends on 1)

The ferroelectric semiconductor device of claim 1, wherein a thickness of the ferroelectric gate layer is 0.1 to 100 nm.

### Claim 6 (depends on 1)

The ferroelectric semiconductor device of claim 1, wherein the blocking layer is doped with Si.

### Claim 7 (depends on 1)

The ferroelectric semiconductor device of claim 1, wherein the semiconductor device has a three dimensional structure.

### Claim 8 (depends on 1)

The ferroelectric semiconductor device of claim 1, wherein the first seed layer includes at least one of ZrO2, Y2O3, HfO2, Ta2O5, or Al2O3.

### Claim 9 (depends on 1)

The ferroelectric semiconductor device of claim 1, wherein the first seed layer includes a bi-layer including an amorphous buffer layer and a crystalline layer.

### Claim 10 (depends on 1)

The ferroelectric semiconductor device of claim 1, wherein the blocking layer includes at least one of HfSiO4, ZrSiO4, Si3N4, SiO2, HfO2 or ZrO2.

### Claim 11 (depends on 10)

The ferroelectric semiconductor device of claim 10, wherein the blocking layer is doped with at least one of Si, Mg, Al, Ca, La, Sr, Gd, N, Sc, or Y, Zr, or compounds thereof.

### Claim 12 (depends on 11)

The ferroelectric semiconductor device of claim 11, wherein the blocking layer is doped with Si.

### Claim 13

A ferroelectric semiconductor device, comprising:
a substrate;
a channel formed in the substrate
a first seed layer disposed over the channel;
a ferroelectric gate layer formed on the first seed layer; and
an electrode formed over the ferroelectric gate layer,
wherein the first seed layer is arranged to increase an orthorhombic phase fraction of the ferroelectric gate layer; and
further comprising a second seed layer disposed on the ferroelectric gate layer, the second seed layer arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.

### Claim 14 (depends on 13)

The ferroelectric semiconductor device of claim 13, further comprising a gate metal disposed on the second seed layer.

### Claim 15 (depends on 14)

The ferroelectric semiconductor device of claim 14, wherein the gate metal is disposed on the second seed layer.

### Claim 16 (depends on 13)

The ferroelectric semiconductor device of claim 13, wherein the first seed layer is arranged to increase a ratio of (O+T+C)/(O+T+C+M), wherein O is the orthorhombic fraction of the ferroelectric gate layer, T is the tetragonal fraction of the ferroelectric gate layer, C is the cubic fraction of the ferroelectric gate layer, and M is the monoclinic fraction of the ferroelectric gate layer.

### Claim 17 (depends on 13)

The ferroelectric semiconductor device of claim 13, wherein the first seed layer includes at least one of ZrO2, Y2O3, HfO2, Ta2O5, or Al2O3.

### Claim 18

A ferroelectric semiconductor device, comprising:
a substrate;
a blocking layer disposed on a channel of the substrate;
a ferroelectric gate layer disposed over the blocking layer;
a seed layer disposed on the ferroelectric gate layer; and
an electrode formed over the ferroelectric gate layer,
wherein the seed layer is arranged to increase an orthorhombic phase fraction of the ferroelectric gate layer and the blocking layer is arranged to increase the band offset between the channel and the blocking layer and to reduce oxygen vacancies between the blocking layer and the channel.

### Claim 19 (depends on 18)

The ferroelectric semiconductor device of claim 18, wherein the first seed layer is arranged to increase the ratio of (O+T+C)/(O+T+C+M), wherein O is the orthorhombic fraction of the ferroelectric gate layer, T is the tetragonal fraction of the ferroelectric gate layer, C is the cubic fraction of the ferroelectric gate layer, and M is the monoclinic fraction of the ferroelectric gate layer.

### Claim 20 (depends on 18)

The ferroelectric semiconductor device of claim 18, wherein the ferroelectric gate layer includes HfxZr1-xO (x from 0 to 1).