# US 12,119,401 B2 · Semiconductor device and methods of forming

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- Number: US 12,119,401 B2
- Document ID: US12119401B2
- Status: Granted
- Kind: B2
- Application number: 18/317,514
- Filed: 2023-05-15
- Published: 2023-09-07
- Granted: 2024-10-15
- Earliest claimed: 2020-10-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hung-Tai Chang; Han-Yu Tang; Ming-Hua Yu; Yee-Chia Yeo
- Web page: https://patentgrep.com/patent/US12119401B2

## CPC

- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/647: {Schottky drain or source electrodes for IGFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In an embodiment, a device includes a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes and a first source/drain region in the first fin and adjacent the first gate spacer, the first source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer having a first dopant concentration of boron. The device also includes and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second dopant concentration of boron, the second dopant concentration being greater than the first dopant concentration.

## Claims

### Claim 1

A device comprising:
a first fin extending from a substrate;
a first gate stack over and along sidewalls of the first fin, the first gate stack being on a top surface of the first fin; and
a first source/drain region in the first fin and adjacent the first gate stack, the first source/drain region comprising:
a first layer on the first fin, the first layer having a first dopant concentration of boron, the first layer extending above the top surface of the first fin, the first layer having a convex top surface; and
a second layer on the first layer, the second layer having a second dopant concentration of boron, the second dopant concentration being greater than the first dopant concentration.

### Claim 2 (depends on 1)

The device of claim 1, further comprising:
a first gate spacer on a sidewall of the first gate stack.

### Claim 3 (depends on 2)

The device of claim 2 further comprising:
an etch stop layer over the first source/drain region and on a sidewall of the first gate spacer;
a first interlayer dielectric over the etch stop layer;
a second interlayer dielectric over the first interlayer dielectric; and
a first conductive contact extending through the first and second interlayer dielectrics and the etch stop layer, the first conductive contact being electrically coupled to the first source/drain region.

### Claim 4 (depends on 2)

The device of claim 2, wherein the second layer physically contacts the first gate spacer.

### Claim 5 (depends on 4)

The device of claim 4, wherein the first layer physically contacts the first gate spacer.

### Claim 6 (depends on 1)

The device of claim 1, further comprising:
a second fin extending from a substrate;
a second gate stack over and along sidewalls of the second fin; and
a second source/drain region in the second fin, the second source/drain region comprising a third layer, the third layer having a different material composition than the first and second layers.

### Claim 7 (depends on 1)

The device of claim 1, wherein the second dopant concentration is from two to ten times greater than the first dopant concentration.

### Claim 8 (depends on 1)

The device of claim 1, wherein the second layer has a flat top surface.

### Claim 9

A device comprising:
a first fin extending from a substrate;
a first gate stack over and along sidewalls of the first fin;
a first source/drain region in the first fin and adjacent the first gate stack, the first source/drain region comprising:
a first layer on the first fin, the first layer having a first dopant concentration of boron; and
a second layer on the first layer, the second layer having a second dopant concentration of boron, the second dopant concentration being greater than the first dopant concentration, the second layer being the outermost layer of the first source/drain region; and
a first conductive contact over and electrically coupled to the first source/drain region, the first conductive contact physically contacting the second layer of the first source/drain region.

### Claim 10 (depends on 9)

The device of claim 9, wherein the second layer has a thickness in a range from 5 nm to 30 nm.

### Claim 11 (depends on 9)

The device of claim 9, wherein the second dopant concentration of boron is from two to ten times greater than the first dopant concentration of boron.

### Claim 12 (depends on 11)

The device of claim 11, wherein the second dopant concentration of boron is in a range from 1021 cm−3 to 1022 cm−3.

### Claim 13 (depends on 9)

The device of claim 9, further comprising:
a first gate spacer on a sidewall of the first gate stack, the first layer of the first source/drain region physically contacting the first gate spacer.

### Claim 14 (depends on 9)

The device of claim 9, further comprising:
an etch stop layer over the first source/drain region;
a first interlayer dielectric over the etch stop layer; and
a second interlayer dielectric over the first interlayer dielectric, the first conductive contact extending through the first and second interlayer dielectrics and the etch stop layer.

### Claim 15

A method comprising:
depositing a first dummy gate over and along sidewalls of a first fin, the first fin extending from a substrate;
forming a first source/drain region in the first fin, the forming the first source/drain region comprising:
epitaxially growing a first layer, the first layer having a first dopant concentration of a first dopant; and
epitaxially growing a second layer on the first layer, the second layer having a second dopant concentration of the first dopant, the second dopant concentration being greater than the first dopant concentration, the second layer being a conformal layer on sidewalls and a top surface of the first layer;
forming an etch stop layer over the first source/drain region;
forming an interlayer dielectric over the etch stop layer; and
forming a first conductive contact over and electrically coupled to the first source/drain region.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first layer is epitaxially grown with a first set of growth conditions for a first period of time, and wherein the second layer is epitaxially grown with the first set of growth conditions for a second period of time, the second period of time being shorter than the first period of time.

### Claim 17 (depends on 15)

The method of claim 15, wherein the first dopant is boron.

### Claim 18 (depends on 15)

The method of claim 15, further comprising:
forming a first gate spacer along a sidewall of the first dummy gate, wherein the second layer physically contacts the first gate spacer.

### Claim 19 (depends on 15)

The method of claim 15, further comprising:
replacing the first dummy gate with a functional gate stack disposed over and along sidewalls of the first fin.

### Claim 20 (depends on 17)

The method of claim 17 further comprising:
forming a second dummy gate over and along sidewalls of a second fin extending upwards from the substrate;
forming a second gate spacer along a sidewall of the second dummy gate;
etching a second recess in the second fin adjacent the second gate spacer;
forming a second source/drain region in the second recess, the second source/drain region comprising a third epitaxial layer, the third epitaxial layer having a different material composition than the first and second layers; and
replacing the second dummy gate with a second functional gate stack disposed over and along sidewalls of the first fin.