# US 12,119,400 B2 · Semiconductor transistor device and method of manufacturing the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,119,400 B2
- Document ID: US12119400B2
- Status: Granted
- Kind: B2
- Application number: 17/714,660
- Filed: 2022-04-06
- Published: 2022-07-21
- Granted: 2024-10-15
- Earliest claimed: 2018-12-20
- Assignees: Infineon Technologies Austria AG
- Applicants: Infineon Technologies Austria AG
- Inventors: Robert Paul Haase; Jyotshna Bhandari; Heimo Hofer; Ling Ma; Ashita Mirchandani; Harsh Naik; Martin Poelzl; Martin Henning Vielemeyer; Britta Wutte
- Web page: https://patentgrep.com/patent/US12119400B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/662: {the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures}
- H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for manufacturing a semiconductor transistor device includes etching a vertical gate trench into a silicon region, depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered, etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench, and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.

## Claims

### Claim 1

A method for manufacturing a semiconductor transistor device, the method comprising:
etching a vertical gate trench into a silicon region;
depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered;
etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench;
etching a vertical contact trench into a source region of the semiconductor transistor device; and
depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material,
wherein the vertical contact trench is etched simultaneously as the etching through of the silicon gate material.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
filling the vertical contact trench with a metal material filler,
wherein an upper end of the metal material filler lies vertically above an upper end of a metal inlay region of the gate electrode.

### Claim 3 (depends on 2)

The method of claim 2, and wherein a thickness which the silicon gate material has prior to the etching through of the silicon gate material is chosen such that the upper side of the interlayer dielectric is uncovered by the etching through of the silicon gate material before the vertical contact trench has been etched to a final depth.

### Claim 4 (depends on 1)

The method of claim 1, wherein the silicon gate material has a uniform width in the vertical gate trench.

### Claim 5 (depends on 1)

The method of claim 1, further comprising forming a field electrode in the gate trench, and wherein the interlayer dielectric is formed to cover the field electrode.

### Claim 6 (depends on 1)

The method of claim 1, wherein the gate electrode is formed to comprise a silicon gate region made of the silicon gate material and a metal inlay region made of the metal material, wherein the silicon gate region forms at least a section of the sidewall of the gate electrode, wherein the metal inlay region extends up from a lower end of the gate electrode, and wherein the silicon gate region forms an upper section of the sidewall of the gate electrode, and wherein the metal inlay region forms a lower section of the sidewall of the gate electrode.

### Claim 7 (depends on 1)

The method of claim 1, wherein the gate electrode is formed to comprise a silicon gate region made of the silicon gate material and a metal inlay region made of a metal material, wherein the silicon gate region forms at least a section of the sidewall of the gate electrode, wherein the metal inlay region extends up from a lower end of the gate electrode, and wherein the metal inlay region comprises a silicide layer which is arranged adjacent to the silicon gate region, so that the metal inlay region is electrically connected to the silicon gate region via the silicide layer.

### Claim 8

A method for manufacturing a semiconductor transistor device, the method comprising:
etching a vertical gate trench into a silicon region;
depositing a silicon gate material on a first interlayer dielectric formed in the vertical gate trench so that an upper side of the first interlayer dielectric is covered;
depositing a second interlayer dielectric on an upper side of the silicon gate material in the vertical trench;
etching through a portion of the second interlayer dielectric in the vertical trench to partly uncover the upper side of the silicon gate material;
etching through the partly uncovered upper side of the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench; and
depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
etching a vertical contact trench into a source region of the semiconductor transistor device; and
filling the vertical contact trench with a metal material filler,
wherein an upper end of the metal material filler lies vertically above an upper end of a metal inlay region of the gate electrode.

### Claim 10 (depends on 9)

The method of claim 9, wherein the vertical contact trench is etched simultaneously as the etching through of the silicon gate material, and wherein a thickness which the silicon gate material has prior to the etching through of the silicon gate material is chosen such that the upper side of the interlayer dielectric is uncovered by the etching through of the silicon gate material before the vertical contact trench has been etched to a final depth.