# US 12,119,398 B2 · Semiconductor device

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- Number: US 12,119,398 B2
- Document ID: US12119398B2
- Status: Granted
- Kind: B2
- Application number: 17/707,564
- Filed: 2022-03-29
- Published: 2022-07-14
- Granted: 2024-10-15
- Earliest claimed: 2017-11-20
- Assignees: Rohm Co., Ltd.
- Applicants: Rohm Co., Ltd.
- Inventors: Taketoshi Tanaka
- Web page: https://patentgrep.com/patent/US12119398B2

## CPC

- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 62/854: further characterised by the dopants
- H10D 64/111: {Field plates}
- H10D 64/411: {for FETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device (1) includes a substrate (2), an electron transit layer (4) disposed on the substrate (2), and an electron supply layer (5) disposed on the electron supply layer (4). The electron transit layer (4) includes a conductive path forming layer (43) in contact with the electron supply layer (5), a first semiconductor region (first nitride semiconductor layer) (41) containing an acceptor-type impurity, and a second semiconductor region (second nitride semiconductor layer) (42) disposed at a position closer to the conductive path forming layer (43) than the first semiconductor region (41) and containing an acceptor-type impurity. The first semiconductor region (41) has a higher acceptor density than the second semiconductor region (42).

## Claims

### Claim 1

A semiconductor device comprising
a substrate,
an electron transit layer disposed on the substrate,
an electron supply layer disposed on the electron transit layer,
a gate portion arranged on the electron supply layer, and
a source electrode and a drain electrode that are disposed so as to sandwich the gate portion and are electrically connected to the electron supply layer, respectively, wherein
the source electrode passes above the gate portion, extends toward the drain electrode side, and faces the drain electrode,
the electron transit layer includes a conductive path forming layer in contact with the electron supply layer, a first semiconductor region containing an acceptor-type impurity, and a second semiconductor region disposed at a position closer to the conductive path forming layer than the first semiconductor region and containing an acceptor-type impurity,
the first semiconductor region has a higher concentration of acceptor impurity than a concentration of acceptor impurity of the second semiconductor region,
the gate portion includes a nitride semiconductor layer formed on the electron supply layer and a gate electrode formed on the nitride semiconductor layer, and
the semiconductor device further comprises
a passivation film covering a surface of the electron supply layer, a side surface of the nitride semiconductor layer, and a side surface and an upper surface of the gate electrode, and
a barrier metal film disposed between the passivation film and the source electrode and formed so as to cover the gate portion, wherein
both sides of the upper surface of a portion of the passivation film covering the gate portion are formed into curved surfaces of a convex shape protruding outward.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the first semiconductor region and the second semiconductor region are each made of a nitride semiconductor, and
the electron supply layer is made of a nitride semiconductor containing Al.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the passivation film reaches the drain electrode.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the conductive path forming layer contains an acceptor-type impurity, and
the acceptor-type impurity in the conductive path forming layer is C.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein a concentration of the acceptor-type impurity in the first semiconductor region is not less than 1×1018 cm−3 and not more than 1×1020 cm−3.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein a concentration of the acceptor-type impurity in the second semiconductor region is not less than 1×1017 cm−3 and not more than 1×1018 cm−3.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the first semiconductor region is disposed on the substrate, and
the second semiconductor region is formed on a front surface of the first semiconductor region which is located on an opposite side to the substrate.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein a two-dimensional electron gas is formed in the conductive path forming layer.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the first semiconductor region and the second semiconductor region each are made of a semiconductor having a semi-insulating property.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein the first semiconductor region is doped with at least one type of impurity selected from the group consisting of Mg and Zn.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10, wherein the second semiconductor region is doped with at least one type of impurity selected from the group consisting of C and Fe.

### Claim 12 (depends on 1)

The semiconductor device according to claim 1, wherein the gate electrode has a narrower width than a width of the nitride semiconductor layer.

### Claim 13

A semiconductor device comprising:
a substrate,
an electron transit layer disposed on the substrate,
an electron supply layer disposed on the electron transit layer,
a gate portion arranged on the electron supply layer, and
a source electrode and a drain electrode that are disposed so as to sandwich the gate portion and are electrically connected to the electron supply layer, respectively, wherein
the source electrode passes above the gate portion, extends toward the drain electrode side, and faces the drain electrode,
the electron transit layer includes a conductive path forming layer in contact with the electron supply layer, a first semiconductor region containing an acceptor-type impurity, and a second semiconductor region disposed at a position closer to the conductive path forming layer than the first semiconductor region and containing an acceptor-type impurity,
the first semiconductor region has a higher concentration of acceptor impurity than a concentration of acceptor impurity of the second semiconductor region, and
the first semiconductor region has a smaller energy difference between an acceptor level and a valence band upper end than an energy difference between an acceptor level and a valence band upper end energy of the second semiconductor region.