# US 12,119,397 B2 · Semiconductor IC device including passivation layer for inactivating a dopant in a p-type semiconductor layer and method of manufacturing the same

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- Number: US 12,119,397 B2
- Document ID: US12119397B2
- Status: Granted
- Kind: B2
- Application number: 17/465,212
- Filed: 2021-09-02
- Published: 2022-11-17
- Granted: 2024-10-15
- Earliest claimed: 2021-05-12
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sunkyu Hwang; Jongseob Kim; Joonyong Kim; Younghwan Park; Junhyuk Park; Jaejoon Oh; Injun Hwang
- Web page: https://patentgrep.com/patent/US12119397B2

## CPC

- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 84/82: of only field-effect components
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/471: {High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/411: {for FETs}
- H10D 84/0123: {Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/147: {the encapsulations being multilayered}
- H10D 84/05: using Group III-V technology
- H10D 84/87: of PN-junction gate FETs
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor integrated circuit device includes: a channel layer, a barrier layer; a first p-type semiconductor layer and a second p-type semiconductor layer, spaced apart from each other on the barrier layer; and a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer. The passivation layer may partially inactivate a dopant of at least one of the first p-type semiconductor layer and the second p-type semiconductor layer.

## Claims

### Claim 1

A semiconductor integrated circuit device comprising:
a channel layer;
a barrier layer on the channel layer and configured to induce a 2-dimensional electron gas (2DEG) in the channel layer;
a first p-type semiconductor layer and a second p-type semiconductor layer spaced apart from each other on the barrier layer; and
a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer,
wherein the passivation layer is configured to partially inactivate at least one of a dopant of the first p-type semiconductor layer or a dopant of the second p-type semiconductor layer.

### Claim 2 (depends on 1)

The semiconductor integrated circuit device of claim 1,
wherein the passivation layer comprises a first portion on the first p-type semiconductor layer and a second portion on the second p-type semiconductor layer, and
a thickness or a material composition of the first portion is different from a thickness or a material composition of the second portion, or
both the thickness and the material composition of the first portion are different than the thickness and the material composition of the second portion.

### Claim 3 (depends on 1)

The semiconductor integrated circuit device of claim 1,
wherein the passivation layer comprises a first passivation layer on the first p-type semiconductor layer and a second passivation layer on the second p-type semiconductor layer and the first passivation layer, and
at least one of the first passivation layer or the second passivation layer is configured to partially inactivate the dopant of at least one of the first p-type semiconductor layer or the second p-type semiconductor layer.

### Claim 4 (depends on 3)

The semiconductor integrated circuit device of claim 3,
wherein the first passivation layer and the second passivation layer partially inactivate the dopant of the first p-type semiconductor layer and the dopant of the second p-type semiconductor layer.

### Claim 5 (depends on 3)

The semiconductor integrated circuit device of claim 3, wherein
the second passivation layer is configured to partially inactivate the dopant of the second p-type semiconductor layer, and
the first passivation layer is configured to prevent inactivation of the dopant of the first p-type semiconductor layer.

### Claim 6 (depends on 1)

The semiconductor integrated circuit device of claim 1,
wherein a thickness of the first p-type semiconductor layer is equal to a thickness of the second p-type semiconductor layer.

### Claim 7 (depends on 1)

The semiconductor integrated circuit device of claim 1,
wherein a thickness of the first p-type semiconductor layer differs from a thickness of the second p-type semiconductor layer.

### Claim 8 (depends on 1)

The semiconductor integrated circuit device of claim 1, further comprising:
a first gate contacting the first p-type semiconductor layer; and
a second gate contacting the second p-type semiconductor layer, wherein
the first gate is partially in the first p-type semiconductor layer or the second gate is partially inserted into the second p-type semiconductor layer, or
both the first gate is partially in the first p-type semiconductor layer and the second gate is partially inserted into the second p-type semiconductor layer.

### Claim 9

A semiconductor integrated circuit device comprising:
a channel layer;
a barrier layer on the channel layer and configured to induce a 2-dimensional electron gas (2DEG) in the channel layer; and
a first p-type semiconductor layer and a second p-type semiconductor layer on an upper surface of the barrier layer and spaced apart from each other in a direction parallel to the upper surface the barrier layer,
wherein an active dopant concentration in the first p-type semiconductor layer differs from an active dopant concentration in the second p-type semiconductor layer.

### Claim 10 (depends on 9)

The semiconductor integrated circuit device of claim 9,
wherein a thickness of the first p-type semiconductor layer is equal to a thickness of the second p-type semiconductor layer.

### Claim 11 (depends on 9)

The semiconductor integrated circuit device of claim 9,
wherein a thickness of the first p-type semiconductor layer differs from a thickness of the second p-type semiconductor layer.

### Claim 12 (depends on 9)

The semiconductor integrated circuit device of claim 9, further comprising:
a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer,
wherein the passivation layer is configured to partially inactivate at least one of a dopant of the first p-type semiconductor layer or a dopant of the second p-type semiconductor layer.

### Claim 13 (depends on 9)

The semiconductor integrated circuit device of claim 9, further comprising:
a first gate contacting the first p-type semiconductor layer; and
a second gate contacting the second p-type semiconductor layer, wherein
the first gate is partially in the first p-type semiconductor layer or the second gate is partially in the second p-type semiconductor layer, or
both the first gate is partially in the first p-type semiconductor layer and the second gate is partially in the second p-type semiconductor layer.