# US 12,119,394 B2 · Method of manufacturing a semiconductor device and a semiconductor device

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- Number: US 12,119,394 B2
- Document ID: US12119394B2
- Status: Granted
- Kind: B2
- Application number: 17/843,601
- Filed: 2022-06-17
- Published: 2022-10-06
- Granted: 2024-10-15
- Earliest claimed: 2020-06-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shahaji B. More; Chien Lin; Cheng-Han Lee; Shih-Chieh Chang; Shu Kuan
- Web page: https://patentgrep.com/patent/US12119394B2

## CPC

- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 50/642: {Chemical etching}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;
forming a sacrificial gate structure over the fin structure;
etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;
laterally etching the second semiconductor layers through the source/drain space;
forming an inner spacer made of a dielectric material on an end of each of the etched second semiconductor layers; and
forming a source/drain epitaxial layer in the source/drain space to cover the inner spacer,
wherein at least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.

### Claim 2 (depends on 1)

The method of claim 1, wherein a lateral end of the etched second semiconductor layers has a curved shape.

### Claim 3 (depends on 1)

The method of claim 1, wherein the second semiconductor layers are laterally etched by wet etching.

### Claim 4 (depends on 3)

The method of claim 3, wherein the wet etching comprises repeating wet etchings using an ammonium hydroxide (NH4OH) solution or a tetramethylammonium hydroxide (TMAH) solution.

### Claim 5 (depends on 1)

The method of claim 1, wherein the inner spacer is formed by:
forming a dielectric layer in the source/drain space; and
etching the dielectric layer, thereby leaving the inner spacer on the end of each of the etched second semiconductor layers remaining.

### Claim 6 (depends on 1)

The method of claim 1, further comprising, before the second semiconductors are laterally etched, forming sidewall spacers on side faces of the sacrificial gate structure,
wherein the sidewall spacers are made of a different material than the inner spacer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the inner spacers include at least one of silicon nitride and silicon oxide.

### Claim 8 (depends on 6)

The method of claim 6, wherein the inner spacers include at least one of SiOC, SiOCN and SiCN.

### Claim 9 (depends on 1)

The method of claim 1, wherein in the etching a source/drain region of the fin structure, the first and second semiconductor layers of the source/drain region of the fin structure are etched.

### Claim 10 (depends on 1)

The method of claim 1, wherein in the etching a source/drain region of the fin structure, the second semiconductor layers of the source/drain region of the fin structure are selectively etched, thereby leaving the first semiconductor layers remaining.

### Claim 11 (depends on 1)

The method of claim 1, further comprising, after the source/drain epitaxial layer is formed:
removing the sacrificial gate structure, thereby exposing a part of the fin structure;
removing the second semiconductor layers from the exposed fin structure, thereby forming channel layers including the first semiconductor layers; and
forming a gate dielectric layer and a gate electrode layer around the channel layers,
wherein the gate electrode layer is isolated from the source/drain epitaxial layer by the inner spacer and the gate dielectric layer.

### Claim 12 (depends on 1)

The method of claim 1, wherein:
the first semiconductor layers are made of SiGe, and
the second semiconductor layers are made of Si.

### Claim 13 (depends on 12)

The method of claim 12, wherein in the at least one of the first semiconductor layers, a Ge concentration at a center region is smaller than a Ge concentration at edge regions along the stacked direction.

### Claim 14

A method of manufacturing a semiconductor device, comprising:
forming a first fin structure and a second fin structure, wherein first semiconductor layers and second semiconductor layers are alternately stacked in each of the first fin structure and the second fin structure;
forming a first sacrificial gate structure over the first fin structure and a second sacrificial gate structure over the second fin structure;
while the second fin structure with the second sacrificial gate structure is protected,
etching a source/drain region of the first fin structure, which is not covered by the first sacrificial gate structure, thereby forming a first source/drain space;
laterally etching the first semiconductor layers in the first source/drain space;
forming a first inner spacer made of a dielectric material on an end of each of the etched first semiconductor layers; and
forming a first source/drain epitaxial layer in the first source/drain space to cover the inner spacer, thereby forming a first structure;
while the first structure is protected,
etching the second semiconductor layers in a source/drain region of the second fin structure, which is not covered by the second sacrificial gate structure, thereby forming a second source/drain space;
laterally etching the second semiconductor layers through the second source/drain space;
forming a second inner spacer made of a dielectric material on an end of each of the etched second semiconductor layers; and
forming a second source/drain epitaxial layer in the second source/drain space to cover the second inner spacer, thereby forming a second structure, wherein:
the first semiconductor layers include Ge, and
in at least one of the first semiconductor layers, a Ge concentration at a center region is smaller than a Ge concentration at edge regions along the stacked direction.

### Claim 15 (depends on 14)

The method of claim 14, wherein:
the first semiconductor layers are made of SiGe, and
the second semiconductor layers are made of Si.

### Claim 16 (depends on 15)

The method of claim 15, wherein the Ge concentration at the center region is in a range from 15% to 35%, and the Ge concentration at the edge regions is in a range from 25% to 50%.

### Claim 17 (depends on 14)

The method of claim 14, wherein:
the first semiconductor layers are made of SiGe,
the second semiconductor layers are made of Si, and
in the at least one of the first semiconductor layers, a Ge concentration has two peaks and a reference Ge concentration region between the two peaks.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
the Ge concentration Gp at the two peaks and the concentration Gr at the reference Ge concentration region satisfy 1.3×Gr≤Gp≤1.7×Gr.

### Claim 19

A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;
forming a sacrificial gate structure over the fin structure;
etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;
laterally etching the second semiconductor layers through the source/drain space;
forming an inner spacer made of a dielectric material on an end of each of the etched second semiconductor layers; and
forming a source/drain epitaxial layer in the source/drain space to cover the inner spacer, wherein:
the first semiconductor layers include Ge, and
in the at least one of the first semiconductor layers, a Ge concentration at a center region is smaller than a Ge concentration at edge regions along the stacked direction.

### Claim 20 (depends on 19)

The method of claim 19, wherein the Ge concentration at the center region is in a range from 15% to 35%, and the Ge concentration at the edge regions is in a range from 25% to 50%.