US 12,119,392 B2 · Semiconductor device and method

Abstract

Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with “all-in-one” silicon (Si) caps.

Claims20

Dependent claims

A method of manufacturing a semiconductor device, the method comprising:

forming a first semiconductor region, the first semiconductor region comprising:
a first core region;
and
a first transition region, wherein the first transition region transitions radially outward from the first core region, the first transition region extending away from the first core region no more than 2 nm;
forming a second semiconductor region, the second semiconductor region comprising:
a second core region, wherein the second core region is a different material from the first core region;
and
a second transition region, wherein the second transition region transitions radially outward from the second core region, the second transition region extending away from the second core region no more than 2 nm;
forming a gate dielectric around the first transition region;
and
forming a gate electrode around the first transition region.

8 more elements

Dependencies are inferred from the claim text.

Semiconductor device and method

Life of this patent

Semiconductor device and method

Life of this patent

Abstract

Claims20