# US 12,119,391 B2 · Fin-based semiconductor device structure including self-aligned contacts and method for forming the same

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- Number: US 12,119,391 B2
- Document ID: US12119391B2
- Status: Granted
- Kind: B2
- Application number: 18/068,388
- Filed: 2022-12-19
- Published: 2023-04-27
- Granted: 2024-10-15
- Earliest claimed: 2021-02-19
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Mao-Lin Huang; Lung-Kun Chu; Chung-Wei Hsu; Jia-Ni Yu; Chun-Fu Lu; Kuo-Cheng Chiang; Kuan-Lun Cheng; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US12119391B2

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01: Manufacture or treatment
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The gate structure includes a gate dielectric layer, a first conductive layer over the first conductive layer. The gate structure includes a fill layer over the first conductive layer. The semiconductor device structure includes a protection layer formed over the fill layer, and a top surface of the gate dielectric layer is lower than a top surface of the protection layer and higher than a top surface of the first conductive layer.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a fin structure formed over a substrate;
a gate structure formed over the fin structure, wherein the gate structure comprises:
a gate dielectric layer;
a first conductive layer over the gate dielectric layer; and
a fill layer over the first conductive layer;
a protection layer formed over the fill layer, wherein a top surface of the gate dielectric layer is lower than a top surface of the protection layer and higher than a top surface of the first conductive layer;
a gate spacer layer formed adjacent to the gate structure; and
an insulating layer formed over the protection layer, wherein the protection layer is separated from the gate spacer layer by the insulating layer, and a top surface of the gate spacer layer is higher than a top surface of the protection layer.

### Claim 2 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a gate contact structure formed over the protection layer, wherein the gate contact structure is electrically connected to the gate structure by the protection layer.

### Claim 3 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein a sidewall of the protection layer is aligned with a sidewall of the gate dielectric layer.

### Claim 4 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a second conductive layer between the first conductive layer and the fill layer, wherein the second conductive layer has a step-shaped structure.

### Claim 5 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a second conductive layer below the first conductive layer, wherein a top surface of the first conductive layer is leveled with a top surface of the second conductive layer.

### Claim 6 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the fill layer is separated from the gate dielectric layer by the first conducive layer.

### Claim 7 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein a sidewall of the protection layer is aligned with a sidewall of the fill layer.

### Claim 8 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the insulating layer comprises a protruding portion in direct contact with the gate dielectric layer.

### Claim 9 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the top surface of the gate dielectric layer is lower than a top surface of the gate spacer layer.

### Claim 10

A semiconductor device structure, comprising:
a fin structure formed over a substrate, wherein the fin structure comprises a plurality of nanostructures;
a gate structure formed over the nanostructures, wherein the gate structure comprises:
a gate dielectric layer formed over the nanostructures;
a first conductive layer formed over the gate dielectric layer, wherein a topmost surface of the first conductive layer is lower than a top surface of the gate dielectric layer;
a fill layer formed over the first conductive layer; and
a protection layer formed over the fill layer, wherein the protection layer is a conductive layer; and
a gate spacer layer formed adjacent to the gate structure, wherein an outer sidewall surface of the gate spacer layer extends beyond a sidewall surface of the protection layer.

### Claim 11 (depends on 10)

The semiconductor device structure as claimed in claim 10,
wherein the top surface of the gate dielectric layer is lower than a top surface of the gate spacer layer.

### Claim 12 (depends on 10)

The semiconductor device structure as claimed in claim 10, wherein the protection layer is not in direct contact with the first conductive layer.

### Claim 13 (depends on 10)

The semiconductor device structure as claimed in claim 10, further comprising:
a second conductive layer between the first conductive layer and the fill layer, wherein the fill layer has a surface in direct contact with a top surface of the first conductive layer and a top surface of the second conductive layer.

### Claim 14 (depends on 10)

The semiconductor device structure as claimed in claim 10, wherein a portion of the fill layer is lower than the topmost surface of the first conductive layer.

### Claim 15 (depends on 10)

The semiconductor device structure as claimed in claim 10, wherein a sidewall of the protection layer is aligned with a sidewall of the gate dielectric layer.

### Claim 16 (depends on 10)

The semiconductor device structure as claimed in claim 10, further comprising:
a second conductive layer formed over the first conductive layer, wherein a portion of the fill layer is embedded in the second conductive layer.

### Claim 17

A method for forming a semiconductor device structure, comprising:
forming a fin structure over a substrate;
forming a dummy gate structure over the fin structure;
forming a dielectric layer over the dummy gate structure;
forming a gate spacer layer adjacent to the dummy gate structure;
removing the dummy gate structure to form a trench in the dielectric layer;
forming a gate dielectric layer in the trench;
forming a first layer over the gate dielectric layer, wherein a top surface of the first layer is lower than a top surface of the gate spacer layer;
forming a fill layer over the first layer;
forming a protection layer over the fill layer; and
forming an insulating layer on the protection layer, wherein a top surface and sidewall surfaces of the protection layer are covered by the insulating layer, and a portion of the insulating layer is in direct contact with the gate spacer layer.

### Claim 18 (depends on 17)

The method for forming the semiconductor device structure as claimed in claim 17, further comprising:
removing a top portion of the fill layer, such that a top surface of the fill layer is leveled with a top surface of the gate dielectric layer.

### Claim 19 (depends on 18)

The method for forming the semiconductor device structure as claimed in claim 18, further comprising:
forming a gate contact structure over the protection layer, wherein a bottom surface of the gate contact structure is lower than a top surface of the gate spacer layer.

### Claim 20 (depends on 17)

The method for forming the semiconductor device structure as claimed in claim 17, further comprising:
forming a second layer between the first layer and the fill layer, wherein the first layer and the second layer are made of different materials.