# US 12,119,390 B2 · Gate spacer structures and methods for forming the same

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- Number: US 12,119,390 B2
- Document ID: US12119390B2
- Status: Granted
- Kind: B2
- Application number: 17/858,968
- Filed: 2022-07-06
- Published: 2022-10-20
- Granted: 2024-10-15
- Earliest claimed: 2019-01-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chun Hsiung Tsai; Clement Hsingjen Wann; Kuo-Feng Yu; Ming-Hsi Yeh; Shahaji B. More; Yu-Ming Lin
- Web page: https://patentgrep.com/patent/US12119390B2

## CPC

- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a gate stack, comprising:
a gate dielectric layer disposed on the substrate; and
a gate electrode disposed on the gate dielectric layer;
a multi-spacer structure, comprising:
a first spacer disposed on a sidewall of the gate stack;
a second spacer comprising a first spacer portion disposed on a sidewall of the first spacer and a second spacer portion disposed on the substrate, wherein the second spacer portion has a thickness that decreases along a top surface of the substrate; and
a third spacer disposed on the second spacer portion and in contact with the substrate; and
a source/drain region formed in the substrate, wherein a portion of the third spacer abuts the source/drain region and the second spacer portion.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the first spacer in a second direction is substantially uniform.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the thickness of the first spacer is between about 3 nm and about 9 nm.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first spacer comprises silicon nitride.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second spacer comprises silicon oxide.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first spacer portion has a thickness in a second direction that is between about 1 nm and about 4 nm.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the portion of the third spacer is disposed on the substrate.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the thickness of the second spacer portion is between about 0 nm and about 4 nm.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the third spacer comprises silicon nitride.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein a distance between the second spacer portion and the source/drain region is greater than about 0.5 nm.

### Claim 11

A semiconductor device, comprising:
a substrate;
a gate stack disposed on the substrate;
a source/drain region disposed in the substrate;
a first spacer formed on a sidewall of the gate stack;
a second spacer, comprising:
a first spacer portion extending in a vertical direction and disposed on a sidewall of the first spacer; and
a second spacer portion extending in a horizontal direction and disposed on the substrate, wherein the second spacer portion comprises a tapered cross-sectional profile; and
a third spacer disposed on and in contact with the substrate and a sidewall of the source/drain region.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the third spacer is in contact with the second spacer portion.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the first, second, and third spacers comprise silicon nitride, silicon oxide, and silicon nitride, respectively.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein the first spacer portion has a thickness between about 1 nm and about 4 nm.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein the second spacer portion has a thickness that decreases away from the gate stack.

### Claim 16

A semiconductor device, comprising:
a substrate;
a gate structure disposed on the substrate;
a first spacer disposed substantially conformally on a sidewall of the gate structure;
a second spacer, comprising:
a first spacer portion disposed substantially conformally on a sidewall of the first spacer; and
a second spacer portion comprising a tapered structure disposed on the substrate and extending laterally from a sidewall of the first spacer portion; and
a third spacer disposed on the second spacer.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, further comprising a source/drain region disposed in the substrate, wherein the third spacer is in physical contact with the substrate and a sidewall of the source/drain region.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, further comprising a source/drain region disposed in the substrate, wherein a portion of the third spacer separates the second spacer portion from a sidewall of the source/drain region.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein top surfaces of the second and third spacers are non-coplanar.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein the first, second, and third spacers comprise silicon nitride, silicon oxide, and silicon nitride, respectively.