# US 12,119,389 B2 · Semiconductor device with reduced trap defect and method of forming the same

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- Number: US 12,119,389 B2
- Document ID: US12119389B2
- Status: Granted
- Kind: B2
- Application number: 18/360,854
- Filed: 2023-07-28
- Published: 2023-11-16
- Granted: 2024-10-15
- Earliest claimed: 2019-07-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Chun Hsiung Tsai; Kuo-Feng Yu; Yu-Ming Lin; Clement Hsingjen Wann
- Web page: https://patentgrep.com/patent/US12119389B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10D 64/01344: {in a nitrogen-containing ambient, e.g. N2O oxidation}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/6526: {introduced into an oxide material, e.g. changing SiO to SiON}
- H10P 14/6532: {by exposure to a plasma}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P 30/40: into insulating materials
- H10W 20/095: {by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096)}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10P 30/22: using masks
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10P 95/062: {involving a dielectric removal step}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; forming fins on the substrate; depositing a dummy gate electrode over the fins; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; performing a first treatment at a first temperature to repair defects in at least one of the dummy gate electrode, the gate spacer and the LDD region; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; depositing an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and subsequent to the forming of the replacement gate, performing a second treatment at a second temperature, lower than the first temperature, to repair defects of the semiconductor device.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
providing a substrate comprising a surface;
forming fins on the substrate;
depositing a dummy gate electrode over the fins;
forming a gate spacer surrounding the dummy gate electrode;
forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer;
performing a first treatment at a first temperature to repair defects in at least one of the dummy gate electrode, the gate spacer and the LDD region;
forming source/drain regions in the respective LDD regions;
removing the dummy gate electrode;
forming a replacement gate to replace the dummy gate electrode;
depositing an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and
subsequent to the forming of the replacement gate, performing a second treatment at a second temperature, lower than the first temperature, to repair defects of the semiconductor device.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming of the dummy gate electrode comprises:
depositing a gate electrode layer over the substrate; and
patterning the gate electrode layer into the dummy gate electrode.

### Claim 3 (depends on 2)

The method of claim 2, wherein the second treatment comprises introducing a hydrogen gas into the semiconductor device.

### Claim 4 (depends on 3)

The method of claim 3, wherein the second treatment is performed at a temperature below about 400° C.

### Claim 5 (depends on 3)

The method of claim 3, wherein the second treatment is performed at a pressure between about 10 atm and about 20 atm.

### Claim 6 (depends on 1)

The method of claim 1, wherein the second treatment is performed subsequent to the depositing of the ILD layer.

### Claim 7 (depends on 1)

The method of claim 1, further comprising depositing a contact plug in the ILD layer, wherein the second treatment is performed subsequent to the depositing of the contact plug.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first treatment introduces a first element to perform the repairing, wherein the first element includes an electronegativity greater than that of a second element introduced in the second treatment.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first treatment and the forming of the LDD regions are performed concurrently.

### Claim 10 (depends on 1)

The method of claim 1, further comprising depositing a first dielectric layer and a second dielectric layer in sequence over the fins prior to the forming of the dummy gate electrode.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first dielectric layer is an oxide layer and the second dielectric layer is a high-k dielectric layer.

### Claim 12 (depends on 1)

The method of claim 1, wherein the forming of the fins on the substrate comprises:
performing an etching operation on the substrate to form strips;
depositing isolation regions between the strips; and
recessing the isolation regions, wherein portions protruding from the isolation regions constitute the fins at upper portions of the respective strips.

### Claim 13 (depends on 1)

The method of claim 1, further comprising depositing a third dielectric layer over the dummy gate electrode and the gate spacer prior to the forming of the LDD regions.

### Claim 14 (depends on 1)

The method of claim 1, further comprising depositing a fourth dielectric layer over the dummy gate electrode and the gate spacer in a conformal manner subsequent to the forming of the LDD regions.

### Claim 15

A method of manufacturing a semiconductor device, comprising:
providing a substrate comprising fins;
forming a dummy gate electrode over the fins;
forming a gate spacer to surround the dummy gate electrode;
depositing a first dielectric layer to cover the gate spacer, the dummy gate electrode and the substrate;
depositing a second dielectric layer over the first dielectric layer;
forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer subsequent to depositing the second dielectric layer;
etching recesses in the substrate through the first dielectric layer and the LDD regions;
forming source/drain regions in the recesses;
removing the second dielectric layer to expose the gate spacer subsequent to forming the source/drain regions;
forming a replacement gate through removing the dummy gate electrode;
forming contact plugs to electrically couple to the replacement gate and the source/drain regions; and
introducing a hydrogen gas to perform a first annealing operation on the semiconductor device.

### Claim 16 (depends on 15)

The method of claim 15, further comprising depositing a dielectric layer stack over the substrate prior to the forming of the dummy gate electrode.

### Claim 17 (depends on 15)

The method of claim 15, further comprising:
depositing a third dielectric layer over the second dielectric layer subsequent to forming the source/drain regions and prior to the forming of the source/drain regions; and
removing the third dielectric layer to expose the second dielectric layer subsequent to forming the source/drain regions.

### Claim 18 (depends on 17)

The method of claim 17, further comprising performing a second anneal operation subsequent to the removing of the second dielectric layer.

### Claim 19 (depends on 17)

The method of claim 17, wherein the forming of the source/drain regions causes a sidewall of the source/drain regions to contact the second dielectric layer.

### Claim 20

A method of manufacturing a semiconductor device, comprising:
providing a semiconductor fin comprising a channel region;
forming a patterned dummy gate over the semiconductor fin;
forming a first dielectric layer over the patterned dummy gate and the channel region;
etching a portion of the first dielectric layer to form a gate spacer;
forming lightly-doped source/drain (LDD) regions in the semiconductor fin on two sides of the patterned dummy gate;
depositing a second dielectric layer over the patterned dummy gate, the gate spacer and the LDD regions;
forming source/drain regions extending through second dielectric layer and the respective LDD regions;
forming a replacement gate in place with the patterned dummy gate;
forming an inter-layer dielectric layer over the source/drain regions and the replacement gate; and
subsequent to the forming of the inter-layer dielectric layer, performing an annealing operation on the semiconductor device in a hydrogen ambient.