# US 12,119,386 B2 · Conductive capping for work function layer and method forming same

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- Number: US 12,119,386 B2
- Document ID: US12119386B2
- Status: Granted
- Kind: B2
- Application number: 17/340,818
- Filed: 2021-06-07
- Published: 2022-09-29
- Granted: 2024-10-15
- Earliest claimed: 2021-03-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Te-Chih Hsiung; Jyun-De Wu; Yi-Chen Wang; Yi-Chun Chang; Yuan-Tien Tu
- Web page: https://patentgrep.com/patent/US12119386B2

## CPC

- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/687: {having cavities, e.g. porous gate dielectrics having gasses therein}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes removing a dummy gate stack to form a first trench between gate spacers, forming a replacement gate stack in the first trench, recessing the replacement gate stack to form a second trench between the gate spacers, selectively depositing a conductive capping layer in the second trench, forming a dielectric hard mask in the second trench and over the conductive capping layer, and etching the dielectric hard mask using an etching gas to form an opening in the dielectric hard mask. The replacement gate stack is revealed to the opening. The conductive capping layer is more resistant to the etching gas than the replacement gate stack. The method further comprises forming a gate contact plug over and contacting the conductive capping layer.

## Claims

### Claim 1

A method comprising:
removing a dummy gate stack to form a first trench between first gate spacers;
forming a first replacement gate stack in the first trench;
recessing the first replacement gate stack to form a second trench between the first gate spacers;
selectively depositing a first conductive capping layer in the second trench, wherein the first conductive capping layer is electrically conductive;
forming a dielectric hard mask in the second trench and over the first conductive capping layer;
etching the dielectric hard mask using an etching gas to form an opening in the dielectric hard mask, wherein the first replacement gate stack is revealed to the opening; and
forming a gate contact plug over and contacting the first conductive capping layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein in the etching, a gate dielectric in the first replacement gate stack is recessed, and sidewalls of the first gate spacers are exposed to the second trench.

### Claim 3 (depends on 1)

The method of claim 1, wherein the depositing the first conductive capping layer comprises:
depositing a first sub layer on the first replacement gate stack; and
depositing a second sub layer over the first sub layer, wherein the first sub layer has a higher conductivity value than the second sub layer.

### Claim 4 (depends on 1)

The method of claim 1 further comprising:
recessing a second replacement gate stack to form a third trench between second gate spacers; and
selectively depositing a second conductive capping layer in the third trench and over the second replacement gate stack, wherein the second conductive capping layer comprises a different material than the first conductive capping layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first replacement gate stack is comprised in a p-type transistor, and the second replacement gate stack is comprised in an n-type transistor, and the first conductive capping layer has a higher work function than the second conductive capping layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first conductive capping layer is more resistant to the etching gas than the first replacement gate stack.

### Claim 7 (depends on 1)

The method of claim 1, wherein after the recessing, the first replacement gate stack has a convex top surface or a concave top surface.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first conductive capping layer is selectively deposited through chemical vapor deposition.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first conductive capping layer is selectively deposited through plating.

### Claim 10

A device comprising:
a semiconductor region;
gate spacers on the semiconductor region;
a gate stack over the semiconductor region and between the gate spacers, wherein the gate stack comprises a plurality of layers;
a conductive capping layer over and contacting the plurality of layers of the gate stack, wherein the conductive capping layer is electrically conductive;
a dielectric hard mask over the conductive capping layer and between the gate spacers; and
a gate contact plug penetrating through the dielectric hard mask to land on the conductive capping layer.

### Claim 11 (depends on 10)

The device of claim 10 further comprising a contact etch stop layer and an inter-layer dielectric over the contact etch stop layer, wherein the gate stack is in the contact etch stop layer and the inter-layer dielectric, and wherein an entirety of the conductive capping layer is lower than top surfaces of the contact etch stop layer and the inter-layer dielectric.

### Claim 12 (depends on 10)

The device of claim 10, wherein the gate stack comprises a gate dielectric and a gate electrode, with the gate dielectric extending underlying and on sidewalls of the gate electrode, wherein the conductive capping layer comprises a portion overlapping the gate dielectric, and wherein the conductive capping layer is separated from the gate dielectric by an air gap.

### Claim 13 (depends on 10)

The device of claim 10, wherein the conductive capping layer comprises tungsten.

### Claim 14 (depends on 10)

The device of claim 10, wherein the conductive capping layer comprises:
a first sub layer contacting the gate stack; and
a second sub layer over the first sub layer, wherein both of the first sub layer and the second sub layer are electrically conductive, and wherein the first sub layer has a higher electrical conductivity value than the second sub layer.

### Claim 15 (depends on 10)

The device of claim 10, wherein the gate stack comprises a concave top surface.

### Claim 16 (depends on 10)

The device of claim 10, wherein the gate stack comprises a convex top surface.

### Claim 17

A device comprising:
an inter-layer dielectric comprising a first top surface;
a source region and a drain region lower than the inter-layer dielectric;
a gate stack between the source region and the drain region, wherein the gate stack is in the inter-layer dielectric, wherein the gate stack comprises a plurality of layers, and each of the layers has a basin shape with a bottom portion and sidewall portions over and joined to the bottom portion;
gate spacers on opposite sidewalls of the gate stack; and
a conductive layer over and contacting top surfaces of the sidewall portions of the plurality of layers, wherein a second top surface of the conductive layer is lower than the first top surface of the inter-layer dielectric and top ends of the gate spacers.

### Claim 18 (depends on 17)

The device of claim 17, wherein an entirety of the conductive layer is between the gate spacers, and wherein a bottom surface of the conductive layer is higher than bottom ends of the gate spacers.

### Claim 19 (depends on 17)

The device of claim 17, wherein the conductive layer comprises a first sub layer comprising a first material and a second sub layer comprising a second material over and contacting the first sub layer, wherein both of the first sub layer and the second sub layer comprise opposite ends in physical contact with the gate spacers.

### Claim 20 (depends on 19)

The device of claim 19 further comprising a dielectric hard mask between the gate spacers, with a third top surface of the dielectric hard mask being coplanar with the top ends of the gate spacers, and wherein a first portion of the dielectric hard mask overlaps a second portion of the conductive layer.