# US 12,119,380 B2 · Method for making semiconductor device including superlattice with oxygen and carbon monolayers

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,119,380 B2
- Document ID: US12119380B2
- Status: Granted
- Kind: B2
- Application number: 18/386,735
- Filed: 2023-11-03
- Published: 2024-02-22
- Granted: 2024-10-15
- Earliest claimed: 2020-07-02
- Assignees: Atomera Incorporated
- Applicants: Atomera Incorporated
- Inventors: Keith Doran Weeks; Nyles Wynn Cody; Marek Hytha; Robert J. Mears; Robert John Stephenson; Hideki Takeuchi
- Web page: https://patentgrep.com/patent/US12119380B2

## CPC

- H10D 62/8162: {having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/798: {being provided in or under the channel regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3238: {being insulating materials}
- H10P 14/3252: {Alternating layers, e.g. superlattice}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.

## Claims

### Claim 1

A method for making a semiconductor device comprising:
forming a superlattice adjacent a semiconductor layer and comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
the at least one non-semiconductor monolayer in a first group of layers of the superlattice comprising oxygen and devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice comprising carbon; and
performing an etch while using the superlattice as an etch stop layer.

### Claim 2 (depends on 1)

The method of claim 1 wherein the second group of layers is above the first group of layers in the superlattice.

### Claim 3 (depends on 1)

The method of claim 1 wherein the semiconductor device comprises a Silicon on Insulator (SOI) semiconductor device.

### Claim 4 (depends on 1)

The method of claim 1 wherein the semiconductor device comprises a Micro-electromechanical System (MEMS) semiconductor device.

### Claim 5 (depends on 1)

The method of claim 1 wherein the second group of layers of the superlattice comprises carbon and is devoid of oxygen.

### Claim 6 (depends on 1)

The method of claim 1 wherein the second group of layers of the superlattice comprises carbon and oxygen.

### Claim 7 (depends on 1)

The method of claim 1 wherein the base semiconductor portion comprises silicon.

### Claim 8

A method for making a semiconductor device comprising:
forming a superlattice adjacent a semiconductor layer and comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
the at least one non-semiconductor monolayer in a first group of layers of the superlattice comprising oxygen and devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice comprising carbon and devoid of oxygen; and
performing an etch while using the superlattice as an etch stop layer.

### Claim 9 (depends on 8)

The method of claim 8 wherein the second group of layers is above the first group of layers in the superlattice.

### Claim 10 (depends on 8)

The method of claim 8 wherein the semiconductor device comprises a Silicon on Insulator (SOI) semiconductor device.

### Claim 11 (depends on 8)

The method of claim 8 wherein the semiconductor device comprises a Micro-electromechanical System (MEMS) semiconductor device.

### Claim 12

A method for making a semiconductor device comprising:
forming a superlattice adjacent a semiconductor layer and comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
the at least one non-semiconductor monolayer in a first group of layers of the superlattice comprising oxygen and devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice comprising carbon and oxygen; and
performing an etch while using the superlattice as an etch stop layer.

### Claim 13 (depends on 12)

The method of claim 12 wherein the second group of layers is above the first group of layers in the superlattice.

### Claim 14 (depends on 12)

The method of claim 12 wherein the semiconductor device comprises a Silicon on Insulator (SOI) semiconductor device.

### Claim 15 (depends on 12)

The method of claim 12 wherein the semiconductor device comprises a Micro-electromechanical System (MEMS) semiconductor device.