# US 12,119,379 B2 · Gate all around transistors with different threshold voltages

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- Number: US 12,119,379 B2
- Document ID: US12119379B2
- Status: Granted
- Kind: B2
- Application number: 18/356,352
- Filed: 2023-07-21
- Published: 2023-11-16
- Granted: 2024-10-15
- Earliest claimed: 2019-09-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jhon Jhy Liaw
- Web page: https://patentgrep.com/patent/US12119379B2

## CPC

- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 84/0128: {Manufacturing their channels}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/364: {of IGFETs}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first gate-all-around (GAA) transistor having a first plurality of channel members, and a second GAA transistor having a second plurality of channel members. A pitch of the first plurality of channel members is substantially identical to a pitch of the second plurality of channel members. The first plurality of channel members has a first channel member thickness (MT1) and the second plurality of channel members has a second channel member thickness (MT2) greater than the first channel member thickness (MT1).

## Claims

### Claim 1

A method, comprising:
forming a first active region and a second active region over a substrate, the first active region and the second active region extending lengthwise along a first direction and spaced apart from one another along a second direction perpendicular to the first direction;
forming a dummy gate stack over channel regions of the first active region and the second active region, the dummy gate stack extending along the second direction;
performing a dummy gate cut process to form a first dielectric feature and a second dielectric feature through the dummy gate stack to define a dummy gate segment sandwiched between the first dielectric feature and the second dielectric feature along the second direction; and
replacing the dummy gate segment with a gate structure.

### Claim 2 (depends on 1)

The method of claim 1,
wherein the substrate comprises a p-type well and an n-type well,
wherein the first active region is disposed over the p-type well,
wherein the second active region is disposed over the n-type well.

### Claim 3 (depends on 1)

The method of claim 1, wherein each of the first active region and the second active region comprises a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers.

### Claim 4 (depends on 3)

The method of claim 3, wherein the replacing of the dummy gate segment comprises:
removing the dummy gate segment;
after the removing, selectively removing the plurality of second semiconductor layers to release the plurality of first semiconductor layers as a plurality of channel members; and
depositing the gate structure to wrap around each of the plurality of channel members.

### Claim 5 (depends on 4)

The method of claim 4, wherein the removing of the dummy gate segment comprises selectively etching the dummy gate segment without substantially etching the first dielectric feature and the second dielectric feature.

### Claim 6 (depends on 4)

The method of claim 4, wherein the replacing of the dummy gate segment further comprises:
after the selectively removing of the plurality of second semiconductor layers, trimming the plurality of channel members to form a plurality of trimmed channel members.

### Claim 7 (depends on 6)

The method of claim 6,
wherein each of the plurality of channel members has a first thickness,
wherein each of the plurality of trimmed channel members has a second thickness,
wherein a ratio of the second thickness to the first thickness is between about 0.75 and about 0.9.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
forming a first well and a second well over the substrate,
wherein the forming of the first active region and the second active region comprises forming the first active region over the first well and the second active region over the second well.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first well is a p-type well and the second well is an n-type well.

### Claim 10

A method, comprising:
forming a first active region over a p-type well of a substrate and a second active region over an n-type well over of the substrate, wherein each of the first active region and the second active region comprises a plurality of silicon layers interleaved by a plurality of silicon germanium layer;
forming a dummy gate stack over channel regions of the first active region and the second active region;
performing a dummy gate cut process to form a first dielectric feature and a second dielectric feature through the dummy gate stack to define a dummy gate segment sandwiched between the first dielectric feature and the second dielectric feature; and
removing the dummy gate stack without substantially etching the first dielectric feature and the second dielectric feature;
selectively removing the plurality of silicon germanium layers in the first active region or the second active region to release the plurality of silicon layers as a first plurality of nanostructures over the p-type well and a second plurality of nanostructures over the n-type well;
thinning the first plurality of nanostructures and the second plurality of nanostructures; and
after the thinning, forming a first gate structure to wrap around each of the first plurality of nanostructures and a second gate structure to wrap around each of the second plurality of nanostructures.

### Claim 11 (depends on 10)

The method of claim 10,
wherein, before the thinning, two adjacent ones of the first plurality of nanostructures are spaced apart by a first spacing,
wherein, after the thinning, the two adjacent ones of the first plurality of nanostructures are spaced apart by a second spacing greater than the first spacing.

### Claim 12 (depends on 11)

The method of claim 11, wherein a ratio of the second spacing to the first spacing is between about 1.05 and about 1.3.

### Claim 13 (depends on 10)

The method of claim 10, wherein the first gate structure comprises an n-type work function metal and the second gate structure comprises a p-type work function metal.

### Claim 14 (depends on 10)

The method of claim 10,
wherein, before the thinning, each the first plurality of nanostructures comprises a first thickness,
wherein, after the thinning, each the first plurality of nanostructures comprises a second thickness,
wherein a ratio of the second thickness to the first thickness is between about 0.75 and about 0.9.

### Claim 15 (depends on 10)

The method of claim 10, wherein the first gate structure is in contact with a second gate structures.

### Claim 16

A method, comprising:
providing a workpiece comprising:
a first stack of semiconductor layers and a second stack of semiconductor layers over a first area of a substrate, each of the first stack and the second stack comprising a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, and
a third stack of semiconductor layers and a fourth stack of semiconductor layers over a second area of the substrate, each of the third stack and the fourth stack comprising the plurality of first semiconductor layers interleaved by the plurality of second semiconductor layers;
forming a first dummy gate stack over the first stack and the second stack;
forming a second dummy gate stack over the third stack and the fourth stack;
performing a gate cut process to form a first dielectric feature and a second dielectric feature such that the first stack and the second stack are disposed between the first dielectric feature and the second dielectric feature, and a third dielectric feature and a fourth dielectric feature such that the third stack and the fourth stack are disposed between the third dielectric feature and the fourth dielectric feature;
selectively removing the first dummy gate stack and the second dummy gate stack without substantially etching the first dielectric feature, the second dielectric feature, the third dielectric feature, and the fourth dielectric feature;
selectively removing the plurality of second semiconductor layers to release the plurality of first semiconductor layers in the first stack, the second stack, the third stack, and the fourth stack as first channel members, second channel members, third channel members, and fourth channel members, respectively;
selectively thinning the first channel members and the second channel members while the third channel members and the fourth channel members are covered by a dielectric filler and a hard mask layer;
after the selectively thinning, removing the dielectric filler and the hard mask layer;
after the removing of the dielectric filler and the hard mask layer, forming a first gate dielectric layer to wrap around the first channel members and the second channel members and a second gate dielectric layer to wrap around the third channel members and the fourth channel members; and
forming a first gate structure to wrap around each of the first channel members, a second gate structure to wrap around each of the second channel members, a third gate structure to wrap around each of the third channel members, and fourth gate structure to wrap around the fourth channel members.

### Claim 17 (depends on 16)

The method of claim 16, wherein the selectively thinning comprises:
depositing the dielectric filler over the first channel members, the second channel members, the third channel members, and the fourth channel members;
planarizing the dielectric filler;
forming the hard mask layer over the dielectric filler to cover the third channel members and the fourth channel members;
after the forming of the hard mask layer, removing the dielectric filler over the first channel members and the second channel members; and
thinning the first channel members and the second channel members.

### Claim 18 (depends on 16)

The method of claim 16,
wherein the first gate structure and the third gate structure comprise an n-type work function metal,
wherein the second gate structure and the fourth gate structure comprise a p-type work function metal.

### Claim 19 (depends on 16)

The method of claim 16, wherein the first gate dielectric layer and the second gate dielectric layer comprise a silicon oxide layer and a high-k dielectric layer.

### Claim 20 (depends on 19)

The method of claim 19, wherein the first gate dielectric layer comprises a first thickness and the second gate dielectric layer comprises a second thickness smaller than the first thickness.