# US 12,119,378 B2 · Methods of forming epitaxial source/drain features in semiconductor devices

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- Number: US 12,119,378 B2
- Document ID: US12119378B2
- Status: Granted
- Kind: B2
- Application number: 17/121,073
- Filed: 2020-12-14
- Published: 2021-05-06
- Granted: 2024-10-15
- Earliest claimed: 2018-08-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jia-Heng Wang; I-Wen Wu; Chen-Ming Lee; Fu-Kai Yang; Mei-Yun Wang
- Web page: https://patentgrep.com/patent/US12119378B2

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/01: Manufacture or treatment
- H10P 14/6308: {of Group IV semiconductors}
- H10P 32/1406: {by ion implantation}
- H10P 32/171: {being group IV material}
- H10P 34/42: with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20)
- H10P 50/283: {by chemical means}
- H10P 50/642: {Chemical etching}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes semiconductor fins disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fins, where a top surface portion of the epitaxial S/D feature includes two surfaces slanted downward toward each other at an angle, a silicide layer disposed conformally over the top portion of the epitaxial S/D feature, and an S/D contact disposed over the silicide layer, where a bottom portion of the S/D contact extends into the epitaxial S/D feature.

## Claims

### Claim 1

A semiconductor structure, comprising:
a first semiconductor fin and a second semiconductor fin disposed over a substrate;
an epitaxial source/drain (S/D) feature disposed over the first and second semiconductor fins, wherein a top portion of the epitaxial S/D feature includes two surfaces slanted downward toward each other at an angle;
a silicide layer disposed conformally over the top portion of the epitaxial S/D feature;
a S/D contact disposed over the silicide layer, wherein a bottom portion of the S/D contact extends into the epitaxial S/D feature; and
an etch-stop layer (ESL), wherein a portion of the ESL extends along and is in direct contact with sidewall surfaces of the epitaxial S/D feature, wherein sidewalls of the S/D contact are partially defined by the ESL,
wherein the epitaxial source/drain feature comprises a first semiconductor layer in direct contact with and merging together the first and second semiconductor fins and a second semiconductor layer wrapping around the first semiconductor layer, and
wherein a concentration of germanium in the second semiconductor layer is no less than twice of a concentration of germanium in the first semiconductor layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein a portion of the S/D contact penetrates into the second semiconductor layer.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, further comprising an interlayer dielectric (ILD) layer disposed over the ESL, wherein the sidewalls of the S/D contact are partially defined by the ILD layer.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the ESL is spaced apart from the first semiconductor layer by the second semiconductor layer, and the ILD layer is spaced apart from the second semiconductor layer by the ESL layer.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, further comprising:
an isolation feature disposed on the substrate and in direct contact with sidewall surfaces of the first and second fins,
wherein the ESL is in direct contact with a top surface of isolation feature.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the epitaxial S/D feature comprises a p-type dopant.

### Claim 7

A semiconductor structure, comprising:
semiconductor fins disposed over a substrate;
an epitaxial source/drain (S/D) feature over the semiconductor fins, wherein the epitaxial S/D feature includes a first Ge-containing layer embedded in a second Ge-containing layer, wherein the first Ge-containing layer merges together the semiconductor fins, and wherein a top surface of the second Ge-containing layer defines a top surface of the epitaxial S/D feature;
an etch stop layer over the substrate and extends along sidewall surfaces of the second Ge-containing layer;
an interlayer dielectric (ILD) layer disposed on the etch stop layer;
a silicide layer contacting the top surface of the epitaxial S/D feature, wherein the silicide layer includes slanted portions that form a downward angle over the top surface of the epitaxial S/D feature; and
a S/D contact disposed in the etch stop layer and the ILD layer to contact the silicide layer.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the top surface of the epitaxial S/D feature includes a first facet and a second facet slanted downward toward each other and away from a sidewall of the epitaxial S/D feature.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein a first distance measured along the first facet is different from a second distance measured along the second facet.

### Claim 10 (depends on 8)

The semiconductor structure of claim 8, wherein the first facet and the second facet are curved surfaces.

### Claim 11 (depends on 7)

The semiconductor structure of claim 7, wherein the downward angle defines a triangular portion of the S/D contact that extends into the epitaxial S/D feature, and wherein a height of the triangular portion is less than a base of the triangular portion.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein a ratio of the height to the base of the triangular portion is about 8/13 to about 2/3.

### Claim 13 (depends on 7)

The semiconductor structure of claim 7, wherein the second Ge-containing layer includes more Ge than the first Ge-containing layer.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein the second Ge-containing layer includes less than about 65% of Ge.

### Claim 15

A semiconductor structure, comprising:
semiconductor fins disposed over a substrate;
a p-type source/drain (S/D) feature disposed over the semiconductor fins, wherein the p-type S/D feature includes a first Ge-containing layer in direct contact with the semiconductor fins and a second Ge-containing layer in direct contact with and surrounding the first Ge-containing layer, and a concentration of germanium in the second Ge-containing layer is no less than twice of a concentration of germanium in the first Ge-containing layer;
an etch-stop layer (ESL) in direct contact with sidewall surfaces of the second Ge-containing layer;
an interlayer dielectric (ILD) layer disposed over the ESL;
a silicide layer contacting a top surface of the p-type S/D feature, wherein the silicide layer includes a first slanted surface and a second slanted surface meeting at an angle; and
a S/D contact disposed in the ILD layer, wherein a bottom portion of the S/D contact is defined by the first and the second slanted surfaces, such that a lowest point of the S/D contact extends downward and away from a sidewall of the S/D contact.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, wherein the second Ge-containing layer has a lower melting point than the first Ge-containing layer.

### Claim 17 (depends on 15)

The semiconductor structure of claim 15, further comprising:
a metal gate structure disposed over the semiconductor fins and adjacent to the p-type S/D feature; and
a dielectric layer disposed between the metal gate structure and the p-type S/D feature.

### Claim 18 (depends on 15)

The semiconductor structure of claim 15, wherein a vertical separation between the lowest point of the S/D contact and a highest point of the silicide layer is less than a lateral separation between sidewalls of the S/D contact.

### Claim 19 (depends on 15)

The semiconductor structure of claim 15, wherein a first distance along the first slanted surface is greater than a second distance along the second slanted surface.

### Claim 20 (depends on 15)

The semiconductor structure of claim 15, wherein the first slanted surface has a curved profile and the second slanted surface has a straight profile.