# US 12,119,377 B2 · SiC devices with shielding structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,377 B2 - Document ID: US12119377B2 - Status: Granted - Kind: B2 - Application number: 17/505,716 - Filed: 2021-10-20 - Published: 2022-06-23 - Granted: 2024-10-15 - Earliest claimed: 2020-12-21 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Michael Hell; Rudolf Elpelt; Caspar Leendertz - Web page: https://patentgrep.com/patent/US12119377B2 ## CPC - H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures} - H10D 8/051: {of Schottky diodes} - H10D 8/60: Schottky-barrier diodes - H10D 12/031: {of IGBTs} - H10D 30/66: Vertical DMOS [VDMOS] FETs - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 30/831: {Vertical FETs having PN junction gate electrodes (Vertical SIT H10D30/202)} - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D 62/126: {Top-view geometrical layouts of the regions or the junctions} - H10D 62/8325: {Silicon carbide} - H10D 64/0123: {to silicon carbide} - H10D 64/01366: {the semiconductor being silicon carbide} - H10P 30/2042: {into crystalline silicon carbide} - H10P 30/21: {of electrically active species} - H10P 30/22: using masks - H10W 10/00: Isolation regions in semiconductor bodies between components of integrated devices - H10W 10/01: {Manufacture or treatment} - H10W 10/031: {of isolation regions comprising PN junctions} - H10W 10/30: Isolation regions comprising PN junctions - H10D 62/343: {Gate regions of field-effect devices having PN junction gates} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes: a SiC substrate; a device structure in or on the SiC substrate and subject to an electric field during operation of the semiconductor device; a current-conduction region of a first conductivity type in the SiC substrate adjoining the device structure; and a shielding region of a second conductivity type laterally adjacent to the current-conduction region and configured to at least partly shield the device structure from the electric field. The shielding region has a higher net doping concentration than the current-conduction region, and has a length (L) measured from a first position which corresponds to a bottom of the device structure to a second position which corresponds to a bottom of the shielding region. The current-conduction region has a width (d) measured between opposing lateral sides of the current-conduction region, and L/d is in a range of 1 to 10. ## Claims ### Claim 1 A semiconductor device, comprising: a SiC substrate; a device structure in or on the SiC substrate and subject to an electric field during operation of the semiconductor device; a current-conduction region of a first conductivity type in the SiC substrate adjoining the device structure; and a shielding region of a second conductivity type laterally adjacent to the current-conduction region and configured to at least partly shield the device structure from the electric field, wherein the shielding region has a higher net doping concentration than the current-conduction region, wherein the shielding region has a length (L) measured from a first position which corresponds to a bottom of the device structure to a second position which corresponds to a bottom of the shielding region, wherein the current-conduction region has a width (d) measured between opposing lateral sides of the current-conduction region, wherein L/d is in a range of 1 to 10. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein L/d is 5 or less. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein Nsh/Ndev is in a range of 1.5 to 100, where Nsh is the net doping concentration of the shielding region and Ndev is the net doping concentration of the current-conduction region. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein Nsh/Ndev is in a range of 3 to 30. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the net doping concentration (Nsh) of the shielding region is greater than Ncrit, where Ncrit=Ecrit·ε0εr/(e·L), Ecrit is a critical electrical field for avalanche breakdown of the SiC substrate, ε0 is vacuum permittivity, εr is a dielectric constant and e is electron charge. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein Nsh/Ncrit is in a range of 1.5 to 100. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the device structure comprises a planar transistor gate structure comprising a gate dielectric on a first main surface of the SiC substrate and a gate electrode separated from the first main surface by the gate dielectric, wherein the current-conduction region adjoins a bottom of the gate dielectric at an interface between the first main surface of the SiC substrate and the gate dielectric, and wherein the first position from which the length of the shielding region is measured corresponds to the bottom of the gate dielectric. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the device structure comprises a trench transistor gate structure comprising a gate trench in the SiC substrate, a gate dielectric lining sidewalls and a bottom of the gate trench, and a gate electrode separated from the SiC substrate by the gate dielectric, wherein the current-conduction region adjoins the bottom of the gate trench, and wherein the first position from which the length of the shielding region is measured corresponds to the bottom of the gate trench. ### Claim 9 (depends on 8) The semiconductor device of claim 8, further comprising a transistor channel region at both sidewalls of the gate trench. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the device structure comprises a metal contact on a first main surface of the SiC substrate, wherein the current-conduction region adjoins the metal contact to form a Schottky junction, and wherein the first position from which the length of the shielding region is measured corresponds to the Schottky junction. ### Claim 11 (depends on 1) The semiconductor device of claim 1, further comprising a superjunction structure that comprises a first region of the first conductivity type below and adjoining the current-conduction region, and a second region of the second conductivity type below and adjoining the shielding region, wherein Na is a doping concentration of the first region and Wa is a width of the first region, wherein Nb is a doping concentration of the second region and Wb is a width of the second region, wherein Na*Wa=Δ*Nb*Wb in a horizontal cross-section of the superjunction structure, and wherein Δ is in a range of 2/3 to 3/2. ### Claim 12 (depends on 1) The semiconductor device of claim 1, wherein the device structure comprises a JFET gate of the second conductivity type, and wherein the current-conduction region adjoins the JFET gate of the second conductivity type. ### Claim 13 A method of producing a semiconductor device, the method comprising: forming a device structure in or on the SiC substrate, the device structure subject to an electric field during operation of the semiconductor device; forming a current-conduction region of a first conductivity type in the SiC substrate adjoining the device structure; and forming a shielding region of a second conductivity type laterally adjacent to the current-conduction region, the shielding region configured to at least partly shield the device structure from the electric field, wherein the current-conduction region and the shielding region are formed such that: the shielding region has a higher net doping concentration than the current-conduction region; the shielding region has a length (L) measured from a first position which corresponds to a bottom of the device structure to a second position which corresponds to a bottom of the shielding region; the current-conduction region has a width (d) measured between opposing lateral sides of the current-conduction region; and L/d is in a range of 1 to 10. ### Claim 14 (depends on 13) The method of claim 13, wherein forming the device structure comprises: forming a gate dielectric on a first main surface of the SiC substrate; and forming a gate electrode on the gate dielectric, wherein the current-conduction region adjoins a bottom of the gate dielectric at an interface between the first main surface of the SiC substrate and the gate dielectric, wherein the first position from which the length of the shielding region is measured corresponds to the bottom of the gate dielectric. ### Claim 15 (depends on 13) The method of claim 13, wherein forming the device structure comprises: etching a gate trench in the SiC substrate; lining sidewalls and a bottom of the gate trench with a gate dielectric; and forming a gate electrode in the gate trench and separated from the SiC substrate by the gate dielectric, wherein the current-conduction region adjoins the bottom of the gate trench, wherein the first position from which the length of the shielding region is measured corresponds to the bottom of the gate trench. ### Claim 16 (depends on 13) The method of claim 13, wherein forming the device structure comprises: forming a metal contact on a first main surface of the SiC substrate, wherein the current-conduction region adjoins the metal contact to form a Schottky junction, wherein the first position from which the length of the shielding region is measured corresponds to the Schottky junction. ### Claim 17 (depends on 13) The method of claim 13, further comprising: forming a superjunction structure that comprises a first region of the first conductivity type below and adjoining the current-conduction region, and a second region of the second conductivity type below and adjoining the shielding region, wherein Na is a doping concentration of the first region and Wa is a width of the first region, wherein Nb is a doping concentration of the second region and Wb is a width of the second region, wherein Na*Wa=Δ*Nb*Wb in a horizontal cross-section of the superjunction structure, and wherein Δ is in a range of 2/3 to 3/2. ### Claim 18 (depends on 13) The method of claim 13, wherein forming the shielding region comprises: implanting dopants of the second conductivity type into the shielding region such that Nsh/Ndev is in a range of 1.5 to 100, where Nsh is the net doping concentration of the shielding region and Ndev is the net doping concentration of the current-conduction region. ### Claim 19 (depends on 13) The method of claim 13, wherein forming the shielding region comprises: implanting dopants of the second conductivity type into the shielding region such that the net doping concentration (Nsh) of the shielding region is greater than Ncrit and Ncrit=Ecrit·ε0εr/(e·L), where Ecrit is a critical electrical field for avalanche breakdown of the SiC substrate, ε0 is vacuum permittivity, εr is a dielectric constant and e is electron charge. ### Claim 20 (depends on 13) The method of claim 13, wherein forming the shielding region comprises: growing a plurality of epitaxial layers of the first conductivity type; and masked implanting of dopants of the second conductivity type into each of the epitaxial layers in a laterally aligned manner. ### Claim 21 (depends on 13) The method of claim 13, wherein forming the shielding region comprises: growing a plurality of epitaxial layers; implanting dopants of one conductivity type into the epitaxial layers; and implanting of dopants of the opposite conductivity type into the epitaxial layers. ### Claim 22 (depends on 13) The method of claim 13, wherein forming the shielding region comprises: growing a single epitaxial layer of the first conductivity type; and implanting dopants of the second conductivity type at energies having multiple peaks or at a continuous energy spectrum.