# US 12,119,376 B2 · Power semiconductor device having vertically parallel p-n layers formed in an active region under transistor cells and under a non-depletable extension zone formed in the edge region

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- Number: US 12,119,376 B2
- Document ID: US12119376B2
- Status: Granted
- Kind: B2
- Application number: 16/587,631
- Filed: 2019-09-30
- Published: 2020-01-23
- Granted: 2024-10-15
- Earliest claimed: 2014-05-14
- Assignees: Infineon Technologies Austria AG
- Applicants: Infineon Technologies Austria AG
- Inventors: Armin Willmeroth; Franz Hirler; Bjoern Fischer; Joachim Weyers
- Web page: https://patentgrep.com/patent/US12119376B2

## CPC

- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/663: {having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS}
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/051: {Forming charge compensation regions, e.g. superjunctions}
- H10D 64/111: {Field plates}
- H02M 1/0054: {Transistor switching losses (periodically suspending operation of switching converter in low power mode H02M1/0035)}
- H02M 3/155: using semiconductor devices only
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS

## Abstract

A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.

## Claims

### Claim 1

A switched-mode power supply comprising a power semiconductor device that comprises:
a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones,
wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device,
wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and
wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.

### Claim 2 (depends on 1)

The switched-mode power supply of claim 1, wherein the drift zone comprises a compensation structure, wherein the compensation structure includes first zones of a first conductivity type and second zones of a second, opposite conductivity type, the first and second zones alternately arranged along a horizontal direction orthogonal to a vertical direction, the vertical direction defined by a direct connection line between one of the transistor cells and the drain layer.

### Claim 3 (depends on 2)

The switched-mode power supply of claim 2, wherein a vertical dopant profile of the first zones includes local maxima between local minima and the local maxima exceed the neighboring local minima by not more than 20%.

### Claim 4 (depends on 2)

The switched-mode power supply of claim 2, wherein the transistor cells are arranged in an active area of the semiconductor body, and an edge area between the active area and a lateral surface of the semiconductor body is devoid of transistor cells.

### Claim 5 (depends on 4)

The switched-mode power supply of claim 4, wherein the edge area comprises at least one of an intrinsic portion, an insulator trench or pairs of superposed first and second zones.

### Claim 6 (depends on 4)

The switched-mode power supply of claim 4, wherein the edge area in total comprises less first and second zones per volume unit than the active area or is devoid of the first and second zones.

### Claim 7 (depends on 4)

The switched-mode power supply of claim 4, further comprising:
an interlayer dielectric structure adjoining a first surface of the semiconductor body and separating, in the edge area, a gate construction from the semiconductor body; and
a non-depletable extension zone in the semiconductor body in a vertical projection of at least a portion of the gate construction, wherein the non-depletable extension zone is of a conductivity type of body zones of the transistor cells and electrically connected to one of the body zones.

### Claim 8 (depends on 7)

The switched-mode power supply of claim 7, wherein
the non-depletable extension zone extends over at least 40% of a vertical projection of the gate construction.

### Claim 9 (depends on 7)

The switched-mode power supply of claim 7, wherein the non-depletable extension zone is electrically connected to a load electrode.

### Claim 10 (depends on 7)

The switched-mode power supply of claim 7, wherein in the non-depletable extension zone an effective dopant dose is greater than 2.5E12 cm−2.

### Claim 11 (depends on 1)

The switched-mode power supply of claim 1, wherein an areal on state resistance of the semiconductor device is less than 1.5 Ohm*mm2 and a breakdown voltage is greater than 600 V.

### Claim 12

A semiconductor device, comprising:
a semiconductor body comprising:
a drain layer extending to a rear surface of the semiconductor body;
a drift zone disposed over the drain layer and having a lower dopant concentration than the drain layer;
an active area comprising one or more transistor cells, each of the transistor cells comprising source zones disposed over the drift zone and extending to a main surface of the semiconductor body that is opposite from the rear surface, and a gate configured to control a conductive channel between the source zones and the drain layer;
wherein the semiconductor device exhibits a first output charge gradient when a voltage between the drain layer and the source zones increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device,
wherein the semiconductor device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and
wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the drift zone comprises a compensation structure, wherein the compensation structure includes first zones of a first conductivity type and second zones of a second, opposite conductivity type, the first and second zones alternately arranged along a horizontal direction that is parallel to the main and rear surfaces, and wherein a vertical dopant profile of the first zones includes local maxima between local minima and the local maxima exceed the neighboring local minima by not more than 20%.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the semiconductor body further comprises an edge area that is devoid of the transistor cells that separates the active area from a lateral surface of the semiconductor body, the lateral surface extending between the main and rear surfaces, and wherein the edge area comprises at least one of an intrinsic portion, an insulator trench or pairs of superposed ones of the first and second zones.