# US 12,119,375 B2 · Silicon epitaxial wafer production method and silicon epitaxial wafer

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- Number: US 12,119,375 B2
- Document ID: US12119375B2
- Status: Granted
- Kind: B2
- Application number: 17/296,279
- Filed: 2019-08-05
- Published: 2022-01-27
- Granted: 2024-10-15
- Earliest claimed: 2018-12-27
- Assignees: Sumco Corporation
- Applicants: Sumco Corporation
- Inventors: Masayuki Ishibashi; Midori Yoshida; Daisuke Maruoka
- Web page: https://patentgrep.com/patent/US12119375B2

## CPC

- H10D 62/405: {Orientations of crystalline planes}
- B24B 7/228: {for grinding thin, brittle parts, e.g. semiconductors, wafers (grinding edges of thin, brittle parts B24B9/065)}
- C23C 16/0254: {Physical treatment to alter the texture of the surface, e.g. scratching or polishing}
- C23C 16/24: Deposition of silicon only
- C23C 16/46: characterised by the method used for heating the substrate (C23C16/48, C23C16/50 take precedence)
- C30B 25/20: the substrate being of the same materials as the epitaxial layer
- C30B 29/06: Silicon
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2926: {Crystal orientations}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 90/129: {by polishing}
- H10P 95/402: {of silicon bodies}
- H10P 14/20: of semiconductor materials
- H10P 52/402: {of semiconductor materials}
- H10P 90/14: {by setting crystal orientation}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B24B: MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING (grinding of gear teeth B23F, of screw-threads B23G1/36; by electro-erosion B23H; abrasive or related blasting B24C; tools for grinding, buffing or sharpening B24D; polishing compositions C09G1/00; abrasives C09K3/14; electrolytic etching or polishing C25F3/00; grinding arrangements for use on assembled railway tracks E01B31/17); DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- C30B: SINGLE-CRYSTAL GROWTH (by using ultra-high pressure, e.g. for the formation of diamonds, B01J3/06); UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL (zone-refining of metals or alloys C22B); PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (casting of metals, casting of other substances by the same processes or devices B22D; working of plastics B29; modifying the physical structure of metals or alloys C21D, C22F); SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (for producing semiconductor devices or parts thereof H10); APPARATUS THEREFOR
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

To provide a silicon epitaxial wafer production method and a silicon epitaxial wafer in which the DIC defects can be suppressed, a silicon epitaxial wafer production method is provided, in which an epitaxial layer is grown in a vapor phase on a principal plane of a silicon single crystal wafer. The principal plane is a {110} plane or a plane having an off-angle of less than 1 degree from the {110} plane. The silicon epitaxial wafer production method includes setting a temperature of the silicon single crystal wafer to 1140° C. to 1165° C. and growing the epitaxial layer in the vapor phase at a growth rate of 0.5 μm/min to 1.7 μm/min.

## Claims

### Claim 1

A method for producing a silicon epitaxial wafer in which an epitaxial layer is grown in a vapor phase on a principal plane of a silicon single crystal wafer, the principal plane being a {110} plane or a plane having an off-angle of less than 1 degree from the {110} plane, the method comprising:
setting a temperature of the silicon single crystal wafer to 1140° C. to 1165° C.; and
growing the epitaxial layer in the vapor phase at a growth rate of 0.5 μm/min to 1.7 μm/min so that a number of microscopic step defects having a height over 3 nm on a surface of the epitaxial layer when observed using a differential interference contrast method is 1.5/300 mm wafer or less.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the principal plane of the silicon single crystal wafer is a plane having the off-angle of more than 0 degrees and less than 1 degree from the {110} plane.

### Claim 3 (depends on 1)

The method according to claim 1, comprising mirror-polishing a surface of the epitaxial layer after growing the epitaxial layer in the vapor phase.

### Claim 4 (depends on 3)

The method according to claim 3, wherein the mirror polishing is performed with a polishing margin of more than 0 μm and 0.2 μm or less using a polishing liquid that contains abrasive grains having a grain diameter of 20 nm or less.

### Claim 5

A silicon epitaxial wafer in which an epitaxial layer is grown on a silicon single crystal substrate having a principal plane that is a {110} plane or a plane having an off-angle of less than 1 degree from the {110} plane, wherein
when observed using a differential interference contrast method, the epitaxial layer has microscopic step defects having a height over 3 nm on a surface of 1.5 counts/300 mm wafer or less, and
when observed using a white-light microscope, the epitaxial layer has a PV value of surface roughness of less than 10 nm.

### Claim 6 (depends on 5)

The silicon epitaxial wafer according to claim 5, wherein the principal plane of the silicon single crystal substrate is a plane having the off-angle of more than 0 degrees and less than 1 degree from the {110} plane.

### Claim 7 (depends on 5)

The silicon epitaxial wafer according to claim 5, wherein the surface of the epitaxial layer has a haze level (measured in SP2, DWO mode) of 0.4 ppm or less.

### Claim 8 (depends on 5)

The silicon epitaxial wafer according to claim 5, wherein the silicon single crystal substrate is a wafer to which boron is added to adjust resistivity to 1 mΩ·cm to 100 mΩ·cm.

### Claim 9 (depends on 1)

The method according to claim 1, wherein when observed using a white-light microscope, the epitaxial layer has a PV value of surface roughness of less than 10 nm.