# US 12,119,373 B2 · High voltage isolated microelectronic device

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- Number: US 12,119,373 B2
- Document ID: US12119373B2
- Status: Granted
- Kind: B2
- Application number: 18/080,976
- Filed: 2022-12-14
- Published: 2023-04-20
- Granted: 2024-10-15
- Earliest claimed: 2020-12-30
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Jeffrey Alan West
- Web page: https://patentgrep.com/patent/US12119373B2

## CPC

- H10D 1/692: {Electrodes}
- H10D 1/684: {the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method forms a first voltage node of a high voltage component of a microelectronic device. The method also forms a plurality of dielectric layers. The method also forms a second voltage node of the high voltage component of the microelectronic device in a fourth position such that the plurality of dielectric layers is between the first voltage node and the second voltage node. During the forming a second voltage node step, a portion of a third layer in the plurality of dielectric layers, in a region outwardly positioned relative to the second voltage node, is removed to expose the second layer, in the plurality of dielectric layers, in the region.

## Claims

### Claim 1

A microelectronic device, comprising:
a first voltage node; a plurality of dielectric layers adjacent the first voltage node; and a second voltage node positioned such that the plurality of dielectric layers are between the first voltage node and the second voltage node, wherein the plurality of dielectric layers includes a first dielectric layer abutting the first voltage node and having a lateral length greater than a length of the first voltage node and including sidewalls extending to a second dielectric layer, the second dielectric layer being in the plurality of dielectric layers and abutting the first dielectric layer, the sidewalls having a profile that is not parallel to sidewalls of the first voltage node.

### Claim 2 (depends on 1)

The microelectronic device of claim 1 wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer.

### Claim 3 (depends on 1)

The microelectronic device of claim 1 wherein the first dielectric layer has a bandgap less than a bandgap of the second dielectric layer.

### Claim 4 (depends on 1)

The microelectronic device of claim 1:
wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer; and
wherein the first dielectric layer has a bandgap less than a bandgap of the second dielectric layer.

### Claim 5 (depends on 4)

The device of claim 4 wherein the second dielectric layer is on a third dielectric layer that has a third thickness greater than the second thickness and a bandgap greater than the bandgap of the second dielectric layer.

### Claim 6 (depends on 2)

The device of claim 2 wherein the first thickness is less than thirty percent of the second thickness.

### Claim 7 (depends on 1)

The device of claim 1 wherein the first dielectric layer includes silicon nitride.

### Claim 8 (depends on 1)

The device of claim 1 wherein the second dielectric layer includes silicon oxynitride.

### Claim 9 (depends on 1)

The device of claim 1, further comprising a third voltage node formed from a same metal layer as the first voltage node, and a recess in the second dielectric layer between the first and third voltage nodes.

### Claim 10 (depends on 9)

The device of claim 9, further comprising a transistor, the third voltage node between the second voltage node and the transistor.

### Claim 11

An integrated circuit, comprising:
a first electrode of a capacitor over a semiconductor substrate;
a second electrode of the capacitor located vertically over the first electrode;
a plurality of dielectric layers between the first and second electrodes, the plurality of dielectric layers including:
a first dielectric layer abutting the second electrode; and
a second dielectric layer abutting the first dielectric layer,
wherein the first dielectric layer extends laterally past the second electrode over the substrate to a recess in the second dielectric layer.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer.

### Claim 13 (depends on 11)

The integrated circuit of claim 11, wherein the first dielectric layer has a bandgap less than a bandgap of the second dielectric layer.

### Claim 14 (depends on 11)

The integrated circuit of claim 11, wherein the second dielectric layer is located on a third dielectric layer that has a bandgap greater than a bandgap of the second dielectric layer.

### Claim 15 (depends on 11)

The integrated circuit of claim 11, wherein a sidewall of the recess has an arcuate or sloped profile.

### Claim 16 (depends on 11)

The integrated circuit of claim 11, further comprising a third electrode spaced apart laterally from the second electrode and conductively connected to the substrate, the recess being between the second electrode and the third electrode.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, further comprising a transistor over and extending into the substrate, the third electrode between the first electrode and the transistor.