# US 12,119,367 B2 · Composite substrate for fabricating III-V photodetector arrays

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- Number: US 12,119,367 B2
- Document ID: US12119367B2
- Status: Granted
- Kind: B2
- Application number: 17/443,380
- Filed: 2021-07-26
- Published: 2022-01-27
- Granted: 2024-10-15
- Earliest claimed: 2020-07-24
- Assignees: University of Southern California; California Institute of Technology; InPi, LLC
- Applicants: University of Southern California
- Inventors: Rehan Rashid Kapadia; Khaled Ahmed; Frank Greer
- Web page: https://patentgrep.com/patent/US12119367B2

## CPC

- H10F 39/011: {Manufacture or treatment of image sensors covered by group H10F39/12}
- H10F 39/018: {of hybrid image sensors}
- H10F 39/80: {Constructional details of image sensors}
- H10F 39/8033: {Photosensitive area}
- H10F 39/809: {of hybrid image sensors}
- H10F 71/1276: {comprising growth substrates not made of Group III-V materials}
- H10F 71/139: {using temporary substrates}
- H10F 77/1248: {having three or more elements, e.g. GaAlAs, InGaAs or InGaAsP}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

A method for forming a composite substrate containing layers of dissimilar materials is provided. The method includes a step of disposing a release layer over a base substrate where the base substrate is composed of a first material. A template layer is attached to the release layer. Characteristically, the template layer is composed of a second material and adapted to form a compound semiconductor device thereon.

## Claims

### Claim 1

A method for forming a composite substrate containing layers of dissimilar materials, the method comprising:
forming a release layer over a base substrate having a buffer layer, the base substrate being composed of a first material;
attaching a metal template layer to the release layer, the metal template layer being composed of a Group III metal;
depositing a capping layer over the metal template layer, the capping layer being composed of a dielectric material;
patterning the metal template layer and the capping layer to form a first composite substrate including a first plurality of separated template units separated by a first plurality of trenches;
annealing the first composite substrate in an ambient gas to form a second composite substrate wherein metal template layer is converted to a first crystalline semiconductor layer which is interposed between the buffer layer and the capping layer; and
removing the capping layer to form a third composite substrate such that the first crystalline semiconductor layer is exposed.

### Claim 2 (depends on 1)

The method of claim 1, wherein the base substrate is a silicon wafer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the ambient gas includes a Group V atom and the first crystalline semiconductor layer is composed of a III-V compound semiconductor.

### Claim 4 (depends on 3)

The method of claim 3, wherein the III-V compound semiconductor is selected from the group consisting of InP, GaAs, InGaAs, AlAs, AlSb, InAs, InN, GaP, GaAs, GaN, AlP, and AlN.

### Claim 5 (depends on 3)

The method of claim 3, wherein the III-V compound semiconductor is grown on the base substrate by templated liquid phase growth.

### Claim 6 (depends on 5)

The method of claim 5, wherein the III-V compound semiconductor is a single crystal.

### Claim 7 (depends on 5)

The method of claim 5, wherein the III-V compound semiconductor is grown in a plurality of regions on the base substrate.

### Claim 8 (depends on 7)

The method of claim 7, wherein the regions all have the same crystal orientation.

### Claim 9 (depends on 1)

The method of claim 1, further comprising selectively growing a second semiconductor layer over the first crystalline semiconductor layer to form a fourth composite substrate.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming a fifth composite substrate by depositing an oxide layer over the second semiconductor layer and which the trenches and then planarization the oxide layer;
forming a sixth composite substrate by selectively removing a portion of oxide layer to form a second set of trenches and growing metal contacts in the second set of trenches; and
forming a seventh composite substrate by singularizing a plurality of compound semiconductor devices wherein the oxide layer, release layer, and buffer layer are etched to a substrate surface of the base substrate.

### Claim 11 (depends on 10)

The method of claim 10, aligning and attaching readout integrated circuits to the seventh composite substrate.

### Claim 12 (depends on 9)

The method of claim 9, wherein at least one compound semiconductor device including the first crystalline semiconductor layer and the second semiconductor layer is formed.

### Claim 13 (depends on 12)

The method of claim 12, wherein a plurality of compound semiconductor devices are formed in different regions on the base substrate.

### Claim 14 (depends on 12)

The method of claim 12, wherein the at least one compound semiconductor device is sensitive to photons.

### Claim 15 (depends on 12)

The method of claim 12, wherein the at least one compound semiconductor device is a photodetector.

### Claim 16 (depends on 12)

The method of claim 12, wherein the compound semiconductor device is a SWIR detector.

### Claim 17 (depends on 12)

The method of claim 12, wherein the compound semiconductor device is designed for LIDAR applications.

### Claim 18

A composite substrate comprising:
a base substrate;
a buffer layer disposed over the base substrate;
a release layer disposed over the buffer layer;
a first crystalline semiconductor layer disposed over the release layer;
a second semiconductor layer disposed over the first crystalline semiconductor layer; and
an oxide layer is disposed over the first crystalline semiconductor layer and the second semiconductor layer.

### Claim 19 (depends on 18)

The composite substrate of claim 18 wherein the base substrate is a silicon wafer.

### Claim 20 (depends on 19)

The composite substrate of claim 19 wherein the release layer is composed of a component selected from the group consisting of Mo, NbN, and TiN.

### Claim 21 (depends on 18)

The composite substrate of claim 18, the buffer layer has a thickness from about 100 to 200 nm and the release layer has a thickness from about 10 to 50 nm.

### Claim 22 (depends on 18)

The composite substrate of claim 18, wherein the first crystalline semiconductor layer is composed of InP, GaAs, InGaAs, AlAs, AlSb, InAs, InN, GaP, GaAs, GaN, AlP, or AlN.

### Claim 23 (depends on 18)

The composite substrate of claim 18, wherein the second semiconductor layer is composed of InGaAs.

### Claim 24 (depends on 23)

The composite substrate of claim 23, wherein a compound semiconductor device includes the first crystalline semiconductor layer and the second semiconductor layer.

### Claim 25 (depends on 24)

The composite substrate of claim 24, wherein the compound semiconductor device is a photodetector.

### Claim 26 (depends on 18)

The composite substrate of claim 18 further comprising metal contacts embedded in the oxide layer.

### Claim 27 (depends on 26)

The composite substrate of claim 26, wherein an ROIC wafer having metal interconnect pads embedded in oxide is bonded to the composite substrate.

### Claim 28 (depends on 27)

The composite substrate of claim 27, wherein the release layer is configured to be removable to release photodetectors bonded to the ROIC wafer.