# US 12,119,366 B2 · Solid state imaging device, solid state imaging device manufacturing method, and electronic apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,366 B2 - Document ID: US12119366B2 - Status: Granted - Kind: B2 - Application number: 16/329,454 - Filed: 2017-08-25 - Published: 2019-07-18 - Granted: 2024-10-15 - Earliest claimed: 2016-09-09 - Assignees: Sony Semiconductor Solutions Corporation - Applicants: Sony Semiconductor Solutions Corporation - Inventors: Naoki Komai - Web page: https://patentgrep.com/patent/US12119366B2 ## CPC - H10F 39/182: {Colour image sensors} - H04N 25/79: Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors - H10F 39/011: {Manufacture or treatment of image sensors covered by group H10F39/12} - H10F 39/018: {of hybrid image sensors} - H10F 39/199: {Back-illuminated image sensors} - H10F 39/8053: {Colour filters} - H10F 39/8063: {Microlenses} - H10F 39/809: {of hybrid image sensors} - H10F 39/811: {Interconnections} - H04N 25/11: Arrangement of colour filter arrays [CFA]; Filter mosaics - H10F 39/8057: {Optical shielding} - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure relates to a solid state imaging device capable of further decreasing a chip size, a solid state imaging device manufacturing method, and an electronic apparatus. A solid state imaging device includes: a semiconductor substrate with a pixel region on which a plurality of pixels is arranged in a planar manner; a wiring layer that is laminated on the semiconductor substrate and is provided with wiring connected to the plurality of pixels; and a support substrate that is bonded to the wiring layer. A plurality of electrode pads used to be electrically connected to an outside is arranged at positions overlapping the pixel region in the wiring layer, and through-holes are provided at positions corresponding to the plurality of electrode pads in the support substrate. The present technology can be applied to, for example, a back side irradiation type CMOS image sensor of a wafer level CSP. ## Claims ### Claim 1 A solid state imaging device, comprising: a semiconductor substrate that is provided with a pixel region on which a plurality of pixels is arranged in a planar manner; a wiring layer that is laminated on the semiconductor substrate and is provided with a plurality of wirings connected to the plurality of pixels; a support substrate that is bonded to the wiring layer and supports the semiconductor substrate, wherein a plurality of electrode pads used to be electrically connected to an outside is arranged at positions overlapping the pixel region in the wiring layer when the semiconductor substrate is viewed in the planar manner; a plurality of through-holes that are provided at positions corresponding to selected electrode pads of the plurality of electrode pads in the support substrate; a through-electrode that is electrically and physically connected to a corresponding selected electrode pad at a bottom surface of a corresponding through-hole of the plurality of through-holes, wherein the plurality of through-holes are each constantly tapered from an upper surface of the support substrate through a lower surface of the support substrate into the wiring layer such that openings of each of the plurality of through-holes at the upper surface of the support substrate are larger than openings of each of the plurality of through-holes at the lower surface of the support substrate; and an insulation film formed on side surfaces of the plurality of through-holes extending into the wiring layer and on an entire surface of the upper surface of the support substrate except for where the plurality of through-holes exists. ### Claim 2 (depends on 1) The solid state imaging device according to claim 1, wherein the plurality of wirings is formed in a multi-layer structure on the wiring layer and an electrode pad layer on which the plurality of electrode pads is arranged is provided on a side of the support substrate in relation to the plurality of wirings. ### Claim 3 (depends on 2) The solid state imaging device according to claim 2, wherein each of the plurality of electrode pads includes a conductor different from that of each of the plurality of wirings. ### Claim 4 (depends on 1) The solid state imaging device according to claim 1, wherein each of the plurality of electrode pads is formed on a same layer as that of one layer of a multi-layer structure on the wiring layer. ### Claim 5 (depends on 4) The solid state imaging device according to claim 4, wherein each of the plurality of electrode pads includes a same conductor as that of each of the plurality of wirings. ### Claim 6 (depends on 1) The solid state imaging device according to claim 1, wherein the through-electrode is formed by burying the through-hole with a conductor. ### Claim 7 (depends on 1) The solid state imaging device according to claim 1, wherein the support substrate in which a conductor corresponding to a through-electrode is buried in the through-hole through an insulation film in advance is bonded to the wiring layer while facing each other and the through-electrode and the electrode pad are bonded to each other by a same conductor. ### Claim 8 (depends on 7) The solid state imaging device according to claim 7, wherein the through-electrode is formed by burying the conductor in a via formed to such a depth that the via does not penetrate the support substrate and thinning the support substrate to project a head of the conductor. ### Claim 9 (depends on 7) The solid state imaging device according to claim 7, wherein the electrode pads are arranged on a front surface of the support substrate to correspond to the through-electrodes. ### Claim 10 (depends on 1) The solid state imaging device according to claim 1, wherein the solid state imaging device is flip-chip bonded to other substrates by using a solder ball formed on a front surface of the support substrate to be electrically connected to the electrode pad. ### Claim 11 (depends on 1) The solid state imaging device according to claim 1, wherein a through-electrode penetrating the support substrate and connected to the electrode pad is formed and then a color filter layer is laminated on the semiconductor substrate. ### Claim 12 (depends on 1) The solid state imaging device according to claim 1, wherein the plurality of electrode pads is arranged in a grid shape when the semiconductor substrate is viewed in the planar manner. ### Claim 13 (depends on 1) The solid state imaging device according to claim 1, wherein the solid state imaging device is of a back side irradiation type in which light received by the pixel is irradiated from a back surface side of the semiconductor substrate. ### Claim 14 (depends on 1) The solid state imaging device according to claim 1, wherein each of the plurality of through-holes is provided within the pixel region. ### Claim 15 A method of manufacturing a solid state imaging device including a semiconductor substrate that is provided with a pixel region on which a plurality of pixels is arranged in a planar manner, a wiring layer that is laminated on the semiconductor substrate and is provided with a plurality of wirings connected to the plurality of pixels, and a support substrate that is bonded to the wiring layer and supports the semiconductor substrate, the method comprising steps of: forming a plurality of electrode pads used to be electrically connected to an outside at positions overlapping the pixel region in the wiring layer when the semiconductor substrate is viewed in the planar manner; forming a plurality of through-holes at positions corresponding to selected electrode pads of the plurality of electrode pads in the support substrate; forming a through-electrode that is electrically and physically connected to a corresponding selected electrode pad at a bottom surface of a corresponding through-hole of the plurality of through-holes, wherein the plurality of through-holes are each constantly tapered from an upper surface of the support substrate through a lower surface of the support substrate into the wiring layer such that openings of each of the plurality of through-holes at the upper surface of the support substrate are larger than openings of each of the plurality of through-holes at the lower surface of the support substrate; and forming an insulation film on side surfaces of the plurality of through-holes extending into the wiring layer and on an entire surface of the upper surface of the support substrate except for where the plurality of through-holes exists. ### Claim 16 (depends on 15) The method of manufacturing a solid state imaging device according to claim 15, wherein each of the plurality of through-holes is provided within the pixel region. ### Claim 17 An electronic apparatus, comprising: a solid state imaging device including: a semiconductor substrate that is provided with a pixel region on which a plurality of pixels is arranged in a planar manner; a wiring layer that is laminated on the semiconductor substrate and is provided with a plurality of wirings connected to the plurality of pixels; a support substrate that is bonded to the wiring layer and supports the semiconductor substrate, wherein a plurality of electrode pads used to be electrically connected to an outside is arranged at positions overlapping the pixel region in the wiring layer when the semiconductor substrate is viewed in the planar manner; a plurality of through-holes that are provided at positions corresponding to selected electrode pads of the plurality of electrode pads in the support substrate; a through-electrode that is electrically and physically connected to a corresponding selected electrode pad at a bottom surface of a corresponding through-hole of the plurality of through-holes, wherein the through-holes are constantly tapered from an upper surface of the support substrate through a lower surface of the support substrate into the wiring layer such that openings of the through-holes at the upper surface of the support substrate are larger than openings of the through-holes at the lower surface of the support substrate; and an insulation film formed on side surfaces of the plurality of through-holes extending into the wiring layer and on an entire surface of the upper surface of the support substrate except for where the plurality of through-holes exists. ### Claim 18 (depends on 17) The electronic apparatus according to claim 17, wherein the through-electrode is formed by burying the through-hole with a conductor. ### Claim 19 (depends on 17) The electronic apparatus according to claim 17, wherein each of the plurality of through-holes is provided within the pixel region.