# US 12,119,365 B2 · Optical semiconductor device with integrated vias implementing inter-die connection

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- Number: US 12,119,365 B2
- Document ID: US12119365B2
- Status: Granted
- Kind: B2
- Application number: 17/550,337
- Filed: 2021-12-14
- Published: 2023-06-15
- Granted: 2024-10-15
- Earliest claimed: 2021-12-14
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Pei Cheng Fan
- Web page: https://patentgrep.com/patent/US12119365B2

## CPC

- H10F 39/809: {of hybrid image sensors}
- H10F 39/018: {of hybrid image sensors}
- H10F 39/8037: {the integrated elements comprising a transistor}
- H10F 39/8053: {Colour filters}
- H10F 39/8063: {Microlenses}
- H10F 39/811: {Interconnections}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0253: {comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10F 39/014: {of CMOS image sensors}
- H10F 39/024: {of coatings or optical elements}
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F 39/807: {Pixel isolation structures}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 90/00: Package configurations
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses an optical semiconductor device. The optical semiconductor device includes a logic die including a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and including a memory cell area and a memory peripheral area, and a first inter-die via positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area and electrically coupled to the logic peripheral circuit area through the first inter-die via, and a second intra-die via positioned in the sensor peripheral area. A height of the first intra-die via is greater than a height of the second intra-die via.

## Claims

### Claim 1

An optical semiconductor device, comprising:
a logic die comprising:
a core circuit area and a logic peripheral circuit area;
a memory die positioned on the logic die and comprising:
a memory cell area and a memory peripheral area; and
a first inter-die via positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area, wherein the first inter-die via has a back end extended to a back surface of the memory die and a front end extended through a front surface of the memory die to the logic die; and
a sensor die positioned on the memory die and comprising:
a sensor pixel area and a sensor peripheral area;
a first intra-die via positioned in the sensor peripheral area and electrically coupled to the logic peripheral circuit area through the first inter-die via, wherein the first intra-die via has a back end extended to a back surface of the sensor die and a front end extended to a front surface of the sensor die; and
a second intra-die via positioned in the sensor peripheral area, wherein the second intra-die via has a back end extended to the back surface of the sensor die and a front end extended toward the front surface of the sensor die;
wherein a height of the first intra-die via is greater than a height of the second intra-die via,
wherein the height of the first intra-die via is equal to a thickness of the sensor die between the front surface and the back surface thereof.

### Claim 2 (depends on 1)

The optical semiconductor device of claim 1, wherein the first intra-die via and the second intra-die via are electrically coupled, wherein each of the first inter-die via, the first intra-die via, and the second intra-die via has a tapered shaped that a width is gradually reduced from the back end to the front end.

### Claim 3 (depends on 1)

The optical semiconductor device of claim 1, wherein the second intra-die via is electrically connected to a conductive line of the sensor die.

### Claim 4 (depends on 1)

The optical semiconductor device of claim 1, wherein the first intra-die via is topographically aligned with the first inter-die via and directly positioned on the first inter-die via, such that the front end of the first intra-die via is aligned with and in contact with the back end of the first inter-die via.

### Claim 5 (depends on 1)

The optical semiconductor device of claim 1, wherein the sensor die comprises:
a dielectric layer positioned on the memory die and defining the front surface of the sensor die at a front surface of the dielectric layer;
a substrate positioned on the dielectric layer of the sensor die and defining the back surface of the sensor die at a back surface of the substrate; and
a sensor unit positioned in the substrate of the sensor die;
wherein the first intra-die via is positioned penetrating along the substrate of the sensor die and the dielectric layer of the sensor die, such that the back end of the first intra-die via is extended to the back surface of the substrate while the front end of the first intra-die via is extended to the front surface of the dielectric layer.

### Claim 6 (depends on 5)

The optical semiconductor device of claim 5, further comprising a transfer gate positioned in the dielectric layer of the sensor die.

### Claim 7 (depends on 6)

The optical semiconductor device of claim 6, further comprising a floating diffusion unit positioned in the substrate of the sensor die and positioned in a drain of the transfer gate.

### Claim 8 (depends on 7)

The optical semiconductor device of claim 7, further comprising a color filter positioned on the substrate of the sensor die and above the sensor unit.

### Claim 9 (depends on 8)

The optical semiconductor device of claim 8, further comprising a micro-lens positioned on the color filter.

### Claim 10 (depends on 9)

The optical semiconductor device of claim 9, further comprising an upper layer positioned between the color filter and the substrate of the sensor die;
wherein the upper layer comprises a bottom anti-reflective coating.

### Claim 11 (depends on 1)

The optical semiconductor device of claim 1, wherein a height ratio of a height of the first intra-die via to a height of the second intra-die via is between about 10:3 and about 5:4.

### Claim 12 (depends on 1)

The optical semiconductor device of claim 1, wherein the first inter-die via comprises:
a filler layer positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area; and
an isolation layer covering two sidewalls of the filler layer.

### Claim 13 (depends on 12)

The optical semiconductor device of claim 12, wherein the first inter-die via comprises a seed layer positioned between the filler layer and the seed layer.

### Claim 14 (depends on 13)

The optical semiconductor device of claim 13, wherein the first inter-die via comprises an adhesion layer positioned between the seed layer and the isolation layer.

### Claim 15 (depends on 14)

The optical semiconductor device of claim 14, wherein the first inter-die via comprises a barrier layer positioned between the adhesion layer and the isolation layer.