# US 12,119,353 B2 · Semiconductor device, electronic component, and electronic device

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- Number: US 12,119,353 B2
- Document ID: US12119353B2
- Status: Granted
- Kind: B2
- Application number: 18/519,294
- Filed: 2023-11-27
- Published: 2024-03-14
- Granted: 2024-10-15
- Earliest claimed: 2017-06-02
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei Yamazaki; Kiyoshi Kato; Tomoaki Atsumi
- Web page: https://patentgrep.com/patent/US12119353B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 41/70: the floating gate being an electrode shared by two or more components
- H10D 86/411: {characterised by materials, geometry or structure of the substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A novel semiconductor device formed with single-polarity circuits using OS transistors is provided. Thus, connection between different layers in a memory circuit is unnecessary. This can reduce the number of connection portions and improve the flexibility of circuit layout and the reliability of the OS transistors. In particular, many memory cells are provided; thus, the memory cells are formed with single-polarity circuits, whereby the number of connection portions can be significantly reduced. Further, by providing a driver circuit in the same layer as the cell array, many wirings for connecting the driver circuit and the cell array can be prevented from being provided between layers, and the number of connection portions can be further reduced. An interposer provided with a plurality of integrated circuits can function as one electronic component.

## Claims

### Claim 1

A semiconductor device comprising:
a cell array comprising a first memory cell and a second memory cell;
a first driver circuit configured to supply a selection signal; and
a second driver circuit configured to write or read out data,
wherein the first memory cell comprises a first transistor and a first capacitor,
wherein the second memory cell comprises a second transistor and a second capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to the first capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to the second capacitor,
wherein each of the first transistor and the second transistor includes a first oxide semiconductor layer and a second oxide semiconductor layer over the first oxide semiconductor layer,
wherein the first transistor includes at least a first channel formation region formed in the second oxide semiconductor layer, a third oxide semiconductor layer over the first channel formation region, a first gate electrode over the third oxide semiconductor layer, and a second gate electrode under the first channel formation region, and
wherein the second transistor includes at least a second channel formation region formed in the second oxide semiconductor layer, a fourth oxide semiconductor layer over the second channel formation region, a third gate electrode over the fourth oxide semiconductor layer, and a fourth gate electrode under the second channel formation region.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the second gate electrode includes a first conductor and a second conductor,
wherein the second conductor is in contact with an inner wall of the first conductor,
wherein the fourth gate electrode includes a third conductor and a fourth conductor, and
wherein the fourth conductor is in contact with an inner wall of the third conductor.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
further comprising a first wiring layer under the second gate electrode, and a second wiring layer under the fourth gate electrode,
wherein the first wiring layer includes a fifth conductor and a sixth conductor,
wherein the sixth conductor is in contact with an inner wall of the fifth conductor,
wherein the second wiring layer includes a seventh conductor and an eighth conductor, and
wherein the eighth conductor is in contact with an inner wall of the seventh conductor.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein the first driver circuit comprises a third transistor, and the second driver circuit comprises a fourth transistor, and
wherein each of the third transistor and the fourth transistor includes a channel formation region formed of an oxide semiconductor layer.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1,
wherein each of the first capacitor and the second capacitor includes an electrode, and
wherein the electrode includes the second oxide semiconductor layer.