# US 12,119,352 B2 · IC structure including porous semiconductor layer in bulk substrate adjacent trench isolation

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- Number: US 12,119,352 B2
- Document ID: US12119352B2
- Status: Granted
- Kind: B2
- Application number: 17/647,176
- Filed: 2022-01-06
- Published: 2023-07-06
- Granted: 2024-10-15
- Earliest claimed: 2022-01-06
- Assignees: GlobalFoundries U.S. Inc.
- Applicants: GlobalFoundries U.S. Inc.
- Inventors: Uzma B. Rana; Steven M. Shank; Anthony K. Stamper
- Web page: https://patentgrep.com/patent/US12119352B2

## CPC

- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10W 10/041: {of isolation regions comprising polycrystalline semiconductor materials}
- H10D 30/6704: {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 10/40: Isolation regions comprising polycrystalline semiconductor materials
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit (IC) structure, a switch and related method, are disclosed. The IC structure includes an active device, e.g., a switch, over a bulk semiconductor substrate, and an isolation structure under the active device in the bulk semiconductor substrate. The isolation structure may include a trench isolation adjacent the active device in the bulk semiconductor substrate, a dielectric layer laterally adjacent the trench isolation and over the active device, and a porous semiconductor layer in the bulk semiconductor substrate under the dielectric layer laterally adjacent the trench isolation. The IC structure employs a lower cost, low resistivity bulk semiconductor substrate rather than a semiconductor-on-insulator (SOI) substrate, yet it has better performance characteristics for RF switches than an SOI substrate.

## Claims

### Claim 1

An integrated circuit (IC) structure, comprising:
an active device over a bulk semiconductor substrate; and
an isolation structure under the active device in the bulk semiconductor substrate, the isolation structure including:
a trench isolation adjacent the active device in the bulk semiconductor substrate,
a dielectric layer laterally adjacent the trench isolation and over the active device,
a porous semiconductor layer in the bulk semiconductor substrate under the dielectric layer laterally adjacent the trench isolation, and
a polycrystalline isolation layer under the active device and the trench isolation, the porous semiconductor layer extending through the polycrystalline isolation layer.

### Claim 2 (depends on 1)

The IC structure of claim 1, wherein the polycrystalline isolation layer includes an endwall contacting the porous semiconductor layer.

### Claim 3 (depends on 1)

The IC structure of claim 1, wherein the porous semiconductor layer includes a sidewall in contact with the polycrystalline isolation layer and the bulk semiconductor substrate.

### Claim 4 (depends on 1)

The IC structure of claim 1, wherein the active device includes an epitaxial region over the polycrystalline isolation layer, wherein the epitaxial region has a resistivity higher than the bulk semiconductor substrate.

### Claim 5 (depends on 4)

The IC structure of claim 4, wherein the bulk semiconductor substrate has a resistivity of less than 4 Ohms per square centimeter (Ω/cm2), and the epitaxial region and the polycrystalline isolation layer have a resistivity of greater than 1000 Ω/cm2.

### Claim 6 (depends on 1)

The IC structure of claim 1, wherein the porous semiconductor layer extends partially under the trench isolation.

### Claim 7 (depends on 1)

The IC structure of claim 1, wherein the active device includes a radio frequency (RF) switch.

### Claim 8 (depends on 1)

The IC structure of claim 1, wherein the porous semiconductor layer and the bulk semiconductor substrate include silicon.

### Claim 9 (depends on 1)

The IC structure of claim 1, wherein the porous semiconductor layer has a depth of between 100 nanometers (nm) to 10 micrometers (μm).

### Claim 10

A radio frequency (RF) switch, comprising:
an active device over a bulk semiconductor substrate; and
an isolation structure under the active device in the bulk semiconductor substrate, the isolation structure including:
a trench isolation adjacent the active device in the bulk semiconductor substrate,
a polycrystalline isolation layer under the active device and the trench isolation,
a dielectric layer laterally adjacent the trench isolation and over the active device, and
a porous semiconductor layer in the bulk semiconductor substrate under the dielectric layer laterally adjacent the trench isolation, the porous semiconductor layer extending through the polycrystalline isolation layer.

### Claim 11 (depends on 10)

The RF switch of claim 10, wherein the porous semiconductor layer includes a sidewall in contact with the polycrystalline isolation layer and the bulk semiconductor substrate.

### Claim 12 (depends on 10)

The RF switch of claim 10, wherein the active device includes an epitaxial region over the polycrystalline isolation layer, wherein the epitaxial region has a resistivity higher than the bulk semiconductor substrate.

### Claim 13 (depends on 12)

The RF switch of claim 12, wherein the bulk semiconductor substrate has a resistivity of less than 4 Ohms per square centimeter (Ω/cm2), and the epitaxial region and the polycrystalline isolation layer have a resistivity of greater than 1000 Ω/cm2.

### Claim 14 (depends on 10)

The RF switch of claim 10, wherein the porous semiconductor layer extends partially under the trench isolation.

### Claim 15 (depends on 10)

The RF switch of claim 10, wherein the porous semiconductor layer and the bulk semiconductor substrate include silicon.