# US 12,119,351 B2 · Semiconductor device having fin-type field effect transistor and method of manufacturing the same

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- Number: US 12,119,351 B2
- Document ID: US12119351B2
- Status: Granted
- Kind: B2
- Application number: 17/508,704
- Filed: 2021-10-22
- Published: 2022-02-10
- Granted: 2024-10-15
- Earliest claimed: 2014-07-14
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dong-Il Bae; Kang-Ill Seo
- Web page: https://patentgrep.com/patent/US12119351B2

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/514: {characterised by the insulating layers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 95/062: {involving a dielectric removal step}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor device includes forming a fin structure on a substrate. A sacrificial layer pattern is formed on the fin structure. An active layer pattern is formed on the sacrificial layer pattern. A dummy gate pattern is formed on the active layer pattern. A spacer is formed on the dummy gate pattern. A source/drain structure is formed on the active layer pattern using an epitaxial growth process. An interlayer dielectric layer is formed on the dummy gate pattern and the active layer pattern. The interlayer dielectric layer is planarized to expose the dummy gate pattern. The dummy gate pattern is removed to expose the active layer pattern and the sacrificial layer pattern. The exposed sacrificial layer pattern is removed to form a through-hole between the exposed active layer pattern and the fin structure, the second portion of the sacrificial layer pattern is not removed.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a fin structure on a substrate, the fin structure extending in a first direction;
forming a sacrificial layer pattern on an upper surface of the fin structure, the sacrificial layer pattern including a first portion and a second portion;
forming an active layer pattern on the sacrificial layer pattern, the active layer pattern including a first portion formed on the first portion of the sacrificial layer pattern and a second portion formed on the second portion of the sacrificial layer pattern;
forming a dummy gate pattern on the first portion of the active layer pattern, the dummy gate pattern extending in a second direction crossing the first direction and covering an upper surface and a sidewall of the first portion of the active layer pattern and a sidewall of the first portion of the sacrificial layer pattern;
forming a spacer on a sidewall of the dummy gate pattern;
forming a source/drain structure on an upper surface of the second portion of the active layer pattern using an epitaxial growth process;
forming an interlayer dielectric layer on the dummy gate pattern and the second portion of the active layer pattern;
planarizing the interlayer dielectric layer to expose the dummy gate pattern;
removing the dummy gate pattern to expose the first portion of the active layer pattern and the first portion of the sacrificial layer pattern; and
removing the exposed first portion of the sacrificial layer pattern to form a through-hole between the exposed first portion of the active layer pattern and the upper surface of the fin structure, the second portion of the sacrificial layer pattern not being remove.

### Claim 2 (depends on 1)

The method of claim 1, wherein the source/drain structure covers the upper surface and a sidewall of the second portion of the active layer pattern.

### Claim 3 (depends on 2)

The method of claim 2, wherein the source/drain structure formed on the sidewall of the second portion of the active layer pattern contacts the spacer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the source/drain structure covers a sidewall of the second portion of the sacrificial layer pattern.

### Claim 5 (depends on 4)

The method of claim 4, wherein the source/drain structure formed on the sidewall of the second portion of the sacrificial layer pattern contacts the spacer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
after the removing the exposed first portion of the sacrificial layer pattern, forming a dielectric layer pattern in the through-hole; and
forming a gate electrode structure on the exposed first portion of the active layer pattern, wherein the gate electrode structure covers an upper surface and a sidewall of the exposed first portion of the active layer pattern.

### Claim 7 (depends on 6)

The method of claim 6, wherein the gate electrode structure covers a sidewall of the dielectric layer pattern.

### Claim 8 (depends on 6)

The method of claim 6, wherein the forming of the gate electrode structure comprises:
forming a gate dielectric layer on the upper surface and the sidewall of the first portion of the active layer pattern and on a sidewall of the dielectric layer pattern;
forming a work-function control layer on the gate dielectric layer; and
forming a metal layer on the work-function control layer.

### Claim 9 (depends on 1)

The method of claim 1, further comprising after the removing the exposed first portion of the sacrificial layer pattern, forming a gate electrode structure surrounding the exposed first portion of the active layer pattern.

### Claim 10 (depends on 9)

The method of claim 9, wherein the gate electrode structure in the through-hole contacts the fin structure.

### Claim 11 (depends on 1)

The method of claim 1, wherein the upper surface of the first portion of the active layer pattern is formed on a same plane as the upper surface of the second portion of the active layer pattern.

### Claim 12 (depends on 1)

The method of claim 1, wherein the removing of the exposed first portion of the sacrificial layer pattern is performed by using a wet etching process.

### Claim 13

A method of manufacturing a semiconductor device, the method comprising:
forming a fin structure on a substrate, the fin structure extending in a first direction;
forming a sacrificial layer pattern on an upper surface of the fin structure, the sacrificial layer pattern including a first portion and a second portion;
forming an active layer pattern on the sacrificial layer pattern, the active layer pattern including a first portion formed on the first portion of the sacrificial layer pattern and a second portion formed on the second portion of the sacrificial layer pattern;
forming a dummy gate pattern on the first portion of the active layer pattern, the dummy gate pattern extending in a second direction crossing the first direction and covering an upper surface and a sidewall of the first portion of the active layer pattern and a sidewall of the first portion of the sacrificial layer pattern;
forming a spacer on a sidewall of the dummy gate pattern;
forming a source/drain structure on an upper surface and a sidewall of the second portion of the active layer pattern and a sidewall of the second portion of the sacrificial layer pattern using an epitaxial growth process;
forming an interlayer dielectric layer on the dummy gate pattern and the second portion of the active layer pattern;
planarizing the interlayer dielectric layer to expose the dummy gate pattern;
removing the dummy gate pattern to expose the first portion of the active layer pattern and the first portion of the sacrificial layer pattern;
removing the exposed first portion of the sacrificial layer pattern to form a through-hole between the exposed first portion of the active layer pattern and the upper surface of the fin structure;
forming a dielectric layer pattern in the through-hole; and
forming a gate electrode structure on the exposed first portion of the active layer pattern, wherein the gate electrode structure covers an upper surface and a sidewall of the exposed first portion of the active layer pattern.

### Claim 14 (depends on 13)

The method of claim 13, wherein the source/drain structure formed on the sidewall of the second portion of the active layer pattern contacts the spacer.

### Claim 15 (depends on 13)

The method of claim 13, wherein the source/drain structure formed on the sidewall of the second portion of the sacrificial layer pattern contacts the spacer.

### Claim 16 (depends on 13)

The method of claim 13, wherein the gate electrode structure contacts a sidewall of the dielectric layer pattern.

### Claim 17 (depends on 13)

The method of claim 13, wherein the forming of the gate electrode structure comprises:
forming a gate dielectric layer on the upper surface and the sidewall of the first portion of the active layer pattern and on a sidewall of the dielectric layer pattern;
forming a work-function control layer on the gate dielectric layer; and
forming a metal layer on the work-function control layer.

### Claim 18 (depends on 13)

The method of claim 13, wherein the gate electrode structure in the through-hole contacts the fin structure.

### Claim 19 (depends on 13)

The method of claim 13, wherein the upper surface of the first portion of the active layer pattern is formed on a same plane as the upper surface of the second portion of the active layer pattern.

### Claim 20 (depends on 13)

The method of claim 13, wherein the removing of the exposed first portion of the sacrificial layer pattern is performed by using a wet etching process.