# US 12,119,350 B2 · Semiconductor structure and method for forming semiconductor structure

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- Number: US 12,119,350 B2
- Document ID: US12119350B2
- Status: Granted
- Kind: B2
- Application number: 17/449,493
- Filed: 2021-09-30
- Published: 2022-09-29
- Granted: 2024-10-15
- Earliest claimed: 2021-03-29
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Kui Zhang; Xin Li; Zhan Ying
- Web page: https://patentgrep.com/patent/US12119350B2

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 84/0165: {the components including complementary IGFETs, e.g. CMOS devices}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/3452: {Microstructure}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor structure includes a base and conductive channel structure which includes first and second conductive channel layers and conductive buffer layer. The first conductive channel layer includes a first conductive channel, first and second doped regions on both sides of the first conductive channel; the second conductive channel layer includes a second conductive channel and third and fourth doped regions on both sides of the second conductive channel; the conductive buffer layer reduces electrical interference between the first and third doped regions. The semiconductor structure further includes a first wire layer disposed on the base extending in a direction and in contact with the second doped region; a second wire layer extending in another direction and in contact with the first and third doped regions; and a gate structure disposed around the first and second conductive channels.

## Claims

### Claim 1

A semiconductor structure comprising:
a base and a conductive channel structure on the base, the conductive channel structure comprising a first conductive channel layer, a conductive buffer layer, and a second conductive channel layer stacked in sequence,
wherein the first conductive channel layer comprises a first conductive channel, a first doped region and a second doped region on both sides of the first conductive channel, wherein the first doped region is close to the second conductive channel layer;
the second conductive channel layer comprises a second conductive channel, and a third doped region and a fourth doped region on both sides of the second conductive channel, wherein the third doped region is close to the first conductive channel layer; and
the conductive buffer layer is configured to reduce electrical interference between the first doped region and the third doped region;
a first wire layer, disposed on the base, extending in a first direction, and in contact with the second doped region in the first direction;
a second wire layer, extending in a second direction, and in contact with the first doped region and the third doped region in the second direction;
a gate structure, disposed around the first conductive channel and the second conductive channel; and
a protective layer, nested on top of all of separate conductive channel structures, in contact with the fourth doped region, and having a via penetrating the protective layer in a direction perpendicular to a surface of the base, the via being filled with the gate structure.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the conductive channel structures are separately provided on the base;
the first wire layer is in contact with the second doped regions in all of the conductive channel structures disposed in the first direction;
the second wire layer is in contact with the first doped regions and the third doped regions in all of the conductive channel structures disposed in the second direction; and
the gate structure also fills a gap between a plane where the first wire layer is disposed and a plane where the second wire layer is disposed.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the base comprises a structure region and a wiring region which is disposed at periphery of the structure region;
a peripheral insulating structure is disposed in the wiring region of the base, the first wire layer and the second wire layer extend into the peripheral insulating structure of the wiring region,
the semiconductor structure further comprises: a first conductive plug and a second conductive plug;
wherein the first conductive plug penetrates the peripheral insulating structure and is in contact with the first wire layer; and
the second conductive plug penetrates a part of an outer peripheral insulating structure and is in contact with the second wire layer.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein an angle between the first direction and the second direction is greater than 0 degree.

### Claim 5 (depends on 3)

The semiconductor structure of claim 3, further comprising:
a third conductive plug, in contact with the fourth doped region; and
a fourth conductive plug, in contact with top of the gate structure.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, comprising:
a height of a contact surface between the conductive buffer layer and the first doped region is lower than a height of a central thickness position of the second wire layer, and is higher than a height of a bottom surface of the second wire layer; and
a height of a contact surface between the conductive buffer layer and the third doped region is higher than the height of the central thickness position of the second wire layer and lower than a height of a top surface of the second wire layer.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein a thickness of the conductive buffer layer is less than ⅓ of a thickness of the second wire layer.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the base comprises a substrate and an isolation layer, the first wire layer is disposed in the substrate, and an isolation layer is disposed on a top surface of the substrate, the first conductive channel layer penetrates the isolation layer and a part of the substrate so that the second doped region is in contact with the first wire layer.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the base comprises a substrate and an isolation layer, the isolation layer is disposed on a top surface of the substrate, and the first wire layer is disposed on a top surface of the isolation layer.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, further comprising: a first insulating layer disposed around the first wire layer.

### Claim 11 (depends on 1)

The semiconductor structure of claim 1, further comprising: a second insulating layer disposed around the second wire layer.

### Claim 12 (depends on 1)

The semiconductor structure of claim 1, wherein a top surface of the protective layer is aligned with a top surface of the second conductive channel layer.

### Claim 13 (depends on 1)

The semiconductor structure of claim 1, wherein one of the first conductive channel layer and the second conductive channel layer is an N-type conductive channel, and the other is a P-type conductive channel.

### Claim 14

A method for forming a semiconductor structure, comprising:
providing a base comprising a structure region and a wiring region, wherein the base comprises a substrate, a first wire layer extending in a first direction and an isolation layer;
forming a first sacrificial layer on the base in the structure region, and forming a peripheral insulating structure on the base in the wiring region;
patterning the first sacrificial layer to form a first channel penetrating through the first sacrificial layer;
forming a second wire layer, which fills the first channel and is partially disposed on the first sacrificial layer, extends into the peripheral insulating structure of the wiring region, and extends in a second direction;
sequentially forming a second sacrificial layer and a protective layer on the base in the structure region;
patterning the second sacrificial layer to form a second channel penetrating through the second sacrificial layer, and projections of the first channel and the second channel on the base overlap with each other;
forming a second conductive channel layer filling the second channel;
patterning a part of the protective layer to expose the second sacrificial layer, and removing the second sacrificial layer and the first sacrificial layer; and
forming a gate structure which fills a gap between a plane where the first wire layer is disposed and a plane where the second wire layer.

### Claim 15 (depends on 14)

The method for forming a semiconductor structure of claim 14, wherein providing the base comprising the structure region and the wiring region comprises: providing a substrate comprising the structure region and the wiring region, forming an isolation layer on the substrate in the structure region, and forming the first wire layer on the isolation layer.

### Claim 16 (depends on 14)

The method for forming a semiconductor structure of claim 14, wherein providing the base comprising the structure region and the wiring region comprises: providing a substrate comprising the structure region and the wiring region, forming the first wire layer by doping the substrate in the structure region, and forming the isolation layer on the substrate in the structure region.

### Claim 17

A method for forming a semiconductor structure, comprising:
providing a base comprising a structure region and a wiring region, wherein the base comprises a substrate, a first wire layer extending in a first direction and an isolation layer;
forming a first sacrificial layer on the base in the structure region, and forming a peripheral insulating structure on the base in the wiring region;
forming a second wire layer which extends into the peripheral insulating structure of the wiring region and extends in a second direction on the first sacrificial layer;
sequentially forming a second sacrificial layer and a protective layer on the base in the structure region;
patterning the protective layer, the second sacrificial layer and the first sacrificial layer to form an opening, and filling the opening to form a conductive channel structure;
patterning a part of the protective layer to expose the second sacrificial layer, and removing the second sacrificial layer and the first sacrificial layer; and
forming a gate structure which fills a gap between a plane where the first wire layer is disposed and a plane where the second wire layer.

### Claim 18 (depends on 17)

The method for forming a semiconductor structure of claim 17, wherein providing the base comprising the structure region and the wiring region comprises: providing a substrate comprising the structure region and the wiring region, forming an isolation layer on the substrate in the structure region, and forming the first wire layer on the isolation layer.

### Claim 19 (depends on 17)

The method for forming a semiconductor structure of claim 17, wherein providing the base comprising the structure region and the wiring region comprises: providing a substrate comprising the structure region and the wiring region, forming the first wire layer by doping the substrate in the structure region, and forming the isolation layer on the substrate in the structure region.