# US 12,119,349 B2 · Semiconductor integrated circuit device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,119,349 B2
- Document ID: US12119349B2
- Status: Granted
- Kind: B2
- Application number: 17/404,639
- Filed: 2021-08-17
- Published: 2021-12-02
- Granted: 2024-10-15
- Earliest claimed: 2019-02-18
- Assignees: Socionext Inc.
- Applicants: Socionext Inc.
- Inventors: Hideyuki Komuro; Tomoya Tsuruta; Yasuhiro Nakaoka
- Web page: https://patentgrep.com/patent/US12119349B2

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/907: {CMOS gate arrays}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 89/10: Integrated device layouts
- H10W 20/0698: {Local interconnections}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/427: {Power or ground buses}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/974: {Layout specifications, i.e. inner core regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A cell row includes an inverter cell having a logic function and a termination cell having no logic function. The termination cell is arranged at one of two ends of the cell row. A gate line and dummy gate lines are arranged in the same layer in a Z direction. Local interconnects are arranged in the same layer in the Z direction. Local interconnects are arranged in the same layer in the Z direction.

## Claims

### Claim 1

A semiconductor integrated circuit device, comprising:
a plurality of cell rows each including a plurality of standard cells aligned in a first direction, wherein
a first cell row which is one of the plurality of cell rows includes a first standard cell having a logic function and a second standard cell having no logic function, the second standard cell being arranged at one or each end of the first cell row, wherein
the first standard cell includes
a first power supply line that extends in the first direction and is configured to supply a first power supply voltage,
a second power supply line that extends in the first direction and is configured to supply a second power supply voltage different from the first power supply voltage,
a first transistor that is a three-dimensional transistor of a first conductive type,
a second transistor that is a three-dimensional transistor of a second conductive type, which is formed at a position higher than the first transistor relative to a depth direction,
a gate line extending in a second direction perpendicular to the first direction and in the depth direction, which serves as a gate of each of the first transistor and the second transistor,
a first local interconnect and a second local interconnect extending in the second direction and connected to a source and a drain of the first transistor, respectively, and
a third local interconnect and a fourth local interconnect extending in the second direction and connected to a source and a drain of the second transistor, respectively;
wherein
the second standard cell includes
a third power supply line that extends in the first direction and is configured to supply the first power supply voltage,
a fourth power supply line that extends in the first direction and is configured to supply the second power supply voltage,
a first dummy transistor that is a three-dimensional transistor of the first conductive type, which is arranged in the depth direction in a same layer as the first transistor,
a second dummy transistor that is a three-dimensional transistor of the second conductive type, which is arranged in the depth direction in a same layer as the second transistor,
a dummy gate line extending in the second direction and the depth direction and arranged in the depth direction in a same layer as the gate line, the dummy gate line configured to serve as a gate of each of the first dummy transistor and the second dummy transistor,
a fifth local interconnect extending in the second direction, and arranged in the depth direction in a same layer as the first local interconnect and the second local interconnect, the fifth local interconnect connected to one of a source or a drain of the first dummy transistor, and
a sixth local interconnect extending in the second direction, and arranged in the depth direction in a same layer as the third local interconnect and the fourth local interconnect, the fifth local interconnect connected to one of a source or a drain of the second dummy transistor; and wherein
the sixth local interconnect overlaps the fifth local interconnect in plan view.

### Claim 2 (depends on 1)

The semiconductor integrated circuit device of claim 1, wherein
a channel portion of the first dummy transistor is arranged in the second direction at a same position as a channel portion of the first transistor, and
a channel portion of the second dummy transistor is arranged in the second direction at a same position as a channel portion of the second transistor.

### Claim 3 (depends on 1)

The semiconductor integrated circuit device of claim 1, wherein
the fifth local interconnect is connected to the third power supply line.

### Claim 4 (depends on 1)

The semiconductor integrated circuit device of claim 1, wherein
the second power supply voltage is supplied to the dummy gate line.

### Claim 5 (depends on 1)

The semiconductor integrated circuit device of claim 1, wherein
the second standard cell includes
a first line arranged in a position higher than the sixth local interconnect relative to the depth direction, and overlapping the fifth local interconnect in plan view, the first line being connected to the fifth local interconnect through a contact.