# US 12,119,348 B2 · Stacked device structures and methods for forming the same

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- Number: US 12,119,348 B2
- Document ID: US12119348B2
- Status: Granted
- Kind: B2
- Application number: 17/242,756
- Filed: 2021-04-28
- Published: 2022-11-03
- Granted: 2024-10-15
- Earliest claimed: 2021-04-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Chung-Liang Cheng; Ying-Hsun Chen
- Web page: https://patentgrep.com/patent/US12119348B2

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/509: {characterised by the material of the inner spacers}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/364: {of IGFETs}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10W 90/00: Package configurations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A complementary metal oxide semiconductor (CMOS) device and method of making including a transistor of a first type formed on a first substrate and a transistor of a second type formed on a second substrate. The CMOS device is formed when the first substrate is bonded to the second substrate.

## Claims

### Claim 1

A complementary metal oxide semiconductor (CMOS) device comprising:
a transistor of a first type comprising:
a pair of gate stacks including a metal layer on a dielectric layer;
a semiconductor layer comprising an active region between the pair of gate stacks; and
a contact via in the dielectric layer contacting the active region of the semiconductor layer between the pair of gate stacks; and
a transistor of a second type bonded to the transistor of the first type and electrically coupled to the transistor of the first type by the contact via, wherein the contact via and the dielectric layer are located between the pair of gate stacks and the transistor of the second type.

### Claim 2 (depends on 1)

The device of claim 1, wherein the transistor of the first type is a gate all around metal oxide semiconductor field effect transistor.

### Claim 3 (depends on 2)

The device of claim 2, wherein the transistor of the second type is a fin field effect transistor (FinFET).

### Claim 4 (depends on 3)

The device of claim 3, wherein the contact via of the transistor of the first type is bonded to a back end of the line (BEOL) metal contact of the transistor of the second type.

### Claim 5 (depends on 2)

The device of claim 2, wherein the gate all around metal oxide semiconductor comprises a type I resistor comprising polysilicon, a type II resistor comprising a metal or a type III resistor comprising lower resistance metal than the type II resistor.

### Claim 6 (depends on 2)

The device of claim 2, wherein the gate all around metal oxide semiconductor comprises a dielectric/metal/dielectric capacitor.

### Claim 7 (depends on 1)

The device of claim 1, further comprising a first redistribution layer located between the transistor of the first type and the transistor of the second type.

### Claim 8 (depends on 7)

The device of claim 7, further comprising a second redistribution layer located between the transistor of the first type and the transistor of the second type.

### Claim 9 (depends on 3)

The device of claim 3, wherein the contact via of the transistor of the first type is bonded to a bottom contact of the transistor of the second type.

### Claim 10 (depends on 1)

The device of claim 1, further comprising a metal-insulating-metal memory.

### Claim 11

An integrated circuit comprising:
complementary metal oxide semiconductor (CMOS) transistors comprising:
transistors of a first type comprising:
a pair of gate stacks including a metal layer on a dielectric layer;
a semiconductor layer comprising an active region between the pair of gate stacks; and
a backside contact in the dielectric layer contacting the active region of the semiconductor layer between the pair of gate stacks; and
transistors of a second type comprising a back end of the line (BEOL) contact,
and wherein the backside contact of the transistors of the first type is bonded to the BEOL contact of the transistors of the second type to form the CMOS transistors,
wherein the backside contact and the dielectric layer are located between the pair of gate stacks and the transistors of the second type.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, further comprising at least one redistribution layer located between the transistors of the first type and the transistors of the second type.

### Claim 13 (depends on 11)

The integrated circuit of claim 11, further comprising a metal-insulator-metal memory portion.

### Claim 14

A semiconductor device, comprising:
a fin-shaped field effect transistor (FinFET) comprising:
an interlayer dielectric (ILD) layer; and
an interconnect in the ILD layer; and
a gate-all-around field effect transistor (GAAFET) bonded to the FinFET, comprising:
a pair of gate stacks including a metal layer on a dielectric layer;
a semiconductor layer comprising an active region between the pair of gate stacks; and
a contact via in the dielectric layer contacting the active region of the semiconductor layer between the pair of gate stacks and electrically coupled to the interconnect of the FinFET, wherein the contact via and the dielectric layer are located between the pair of gate stacks and the FinFET.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the FinFET further comprises:
an active region electrically coupled to the interconnect of the FinFET;
a channel region adjacent the active region of the FinFET; and
a gate stack on the channel region, wherein the contact via is located over the gate stack of the FinFET.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the GAAFET further comprises a channel region and the active region is adjacent the channel region.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the channel region of the GAAFET comprises a plurality of channel regions and the active region of the GAAFET is located between the plurality of channel regions.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the plurality of channel regions comprises an insulating layer, and the contact via comprises a first portion having a first width contacting the insulating layer and a second portion having a second width less than the first width contacting the active region of the GAAFET.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein each channel region of the plurality of channel regions comprises a plurality of silicon layers and a dielectric spacer layer on the plurality of silicon layers, and the active region of the GAAFET contacts the dielectric spacer layer.

### Claim 20 (depends on 14)

The semiconductor device of claim 14, further comprising:
a back end of line (BEOL) metal routing on the GAAFET.