# US 12,119,346 B2 · Vertical field-effect transistor with wrap-around contact structure

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- Number: US 12,119,346 B2
- Document ID: US12119346B2
- Status: Granted
- Kind: B2
- Application number: 17/480,717
- Filed: 2021-09-21
- Published: 2023-03-30
- Granted: 2024-10-15
- Earliest claimed: 2021-09-21
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Shogo Mochizuki; Juntao Li
- Web page: https://patentgrep.com/patent/US12119346B2

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 84/834: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A vertical field-effect transistor device includes a substrate comprising a semiconductor material, and a set of fins formed from the semiconductor material and extending vertically with respect to the substrate. The vertical field-effect transistor device further includes gate structures disposed on the substrate and on a portion of sidewalls of the set of fins, spacers disposed on the gate structures and on a remaining portion of the sidewalls of the set of fins, source/drain regions disposed over top portions of the set of fins, and a metal liner disposed adjacent and over the source/drain regions such that a wrap-around contact is defined to cover an upper area of the source/drain regions. A portion of the source/drain regions is configured to have a lateral width less than a width between adjacent gate structures on the respective fin.

## Claims

### Claim 1

A vertical field-effect transistor device, comprising:
a substrate comprising a semiconductor material;
a first fin and a second fin each formed from the semiconductor material and extending vertically with respect to the substrate;
gate structures disposed on the substrate and on a portion of sidewalls of the first fin and the second fin;
spacers disposed on the gate structures and on a remaining portion of the sidewalls of the first fin and the second fin;
a dielectric fill disposed between opposing sidewalls of the spacers and within the gate structures, wherein a top surface of outer ends of the dielectric fill is above a top-most surface of the spacers;
source/drain regions disposed over top portions of the first fin and the second fin; and
a metal liner disposed within the dielectric fill and adjacent and over the source/drain regions such that a wrap-around contact is defined to cover an upper area of the source/drain regions, wherein the wrap-around contact is isolated from the gate structures by the dielectric fill.

### Claim 2 (depends on 1)

The vertical field-effect transistor device according to claim 1, wherein the semiconductor material is silicon.

### Claim 3 (depends on 1)

The vertical field-effect transistor device according to claim 1, further comprising another source/drain region disposed in the substrate and adjacent the first fin and the second fin.

### Claim 4 (depends on 1)

The vertical field-effect transistor device according to claim 1, further comprising a conductive material disposed over the metal liner directly above the source/drain regions disposed over the top portions of the first fin and the second fin.

### Claim 5 (depends on 1)

The vertical field-effect transistor device according to claim 1, wherein the source/drain regions disposed over the top portions of the first fin and the second fin comprise a diamond shaped configuration.

### Claim 6 (depends on 1)

The vertical field-effect transistor device according to claim 1, wherein the gate structures comprise a dielectric layer and a work function metal.

### Claim 7 (depends on 1)

The vertical field-effect transistor device according to claim 1, wherein the first fin and the second fin extend above a top surface of the spacers.

### Claim 8 (depends on 1)

The vertical field-effect transistor device according to claim 1, further comprising an interlevel dielectric layer disposed on opposite sides of the metal liner to define the upper area.

### Claim 9

An integrated circuit, comprising:
a plurality of semiconductor devices, wherein at least one of the plurality of semiconductor devices comprises a vertical field-effect transistor device comprising:
a substrate comprising a semiconductor material;
a first fin and a second fin each formed from the semiconductor material and extending vertically with respect to the substrate;
gate structures disposed on the substrate and on a portion of sidewalls of the first fin and the second fin;
spacers disposed on the gate structures and on a remaining portion of the sidewalls of the first fin and the second fin;
a dielectric fill disposed between opposing sidewalls of the spacers and within the gate structures, wherein a top surface of outer ends of the dielectric fill is above a top-most surface of the spacers;
source/drain regions disposed over top portions of the first fin and the second fin; and
a metal liner disposed within the dielectric fill and adjacent and over the source/drain regions such that a wrap-around contact is defined to cover an upper area of the source/drain regions, wherein the wrap-around contact is isolated from the gate structures by the dielectric fill.

### Claim 10 (depends on 9)

The integrated circuit according to claim 9, wherein the semiconductor material is silicon.

### Claim 11 (depends on 9)

The integrated circuit according to claim 9, further comprising another source/drain region disposed in the substrate and adjacent the first fin and the second fin.

### Claim 12 (depends on 9)

The integrated circuit according to claim 9, further comprising a conductive material disposed over the metal liner directly above the source/drain regions disposed over the top portions of the first fin and the second fin.

### Claim 13 (depends on 9)

The integrated circuit according to claim 9, wherein the source/drain regions disposed over the top portions of the first fin and the second fin comprise a diamond shaped configuration.

### Claim 14 (depends on 9)

The integrated circuit according to claim 9, wherein the gate structures comprise a dielectric layer and a work function metal.

### Claim 15 (depends on 9)

The integrated circuit according to claim 9, wherein the first fin and the second fin extend above a top surface of the spacers.

### Claim 16 (depends on 9)

The integrated circuit according to claim 9, further comprising an interlevel dielectric layer disposed on opposite sides of the metal liner to define the upper area.

### Claim 17

A method for fabricating a vertical field-effect transistor device, comprising:
patterning a substrate comprising a semiconductor material;
forming a first fin and a second fin each comprising the semiconductor material and extending vertically with respect to the substrate;
forming gate structures on the substrate and on a portion of sidewalls of the first fin and the second fin;
forming spacers on the gate structures and on a remaining portion of the sidewalls of the first fin and the second fin;
forming a dielectric fill between opposing sidewalls of the spacers and within the gate structures, wherein a top surface of outer ends of the dielectric fill is above a top-most surface of the spacers;
forming source/drain regions over top portions of the first fin and the second fin; and
forming a metal liner within the dielectric fill and adjacent and over the source/drain regions such that a wrap-around contact is defined to cover an upper area of the source/drain regions, wherein the wrap-around contact is isolated from the gate structures by the dielectric fill.

### Claim 18 (depends on 17)

The method according to claim 17, wherein the source/drain regions comprise a diamond shaped configuration.

### Claim 19 (depends on 1)

The vertical field-effect transistor device according to claim 1, wherein the opposing sidewalls are vertical opposing sidewalls.

### Claim 20 (depends on 9)

The integrated circuit according to claim 9, wherein the opposing sidewalls are vertical opposing sidewalls.